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參數(shù)資料
| 型號(hào)： | SDA9280 |
| 廠商： | SIEMENS A G |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | ICs for Consumer Electronics |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQCC68 |
| 文件頁數(shù)： | 16/43頁 |
| 文件大小： | 249K |
| 代理商： | SDA9280 |
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SDA 9280 B22
Semiconductor Group
16
1998-02-01
This realization does not effect the horizontal detail resolution of the picture because no
filtering is executed.
The highest read frequency is 4/3 of the CLL-frequency for signal compression, the
lowest is 3/4 of the CLL-frequency for signal expansion. The reading clock is supplied by
the internal PLL.
The compander operation mode is programmable via
Ι
2
C signals COMP and COMEX.
Note
: Positioning of a 4:3-signal on a 16:9-screen is realized by delaying the HS-signal.
HS also controls the deflection circuit. In the Siemens MEGAVISION
System a
programmable HS-delay is available in the Memory Sync Controller (MSC) circuit.
2.7
Oversampling, Interpolator 2
Figure 6
Frequency Response of Interpolator 2
(
s
is the sampling frequency at the output of the interpolation filter)
In general D/A conversion requires postfiltering to avoid non-harmonic distortions
caused by intermodulations of the signal with its spectral images. These
intermodulations may come from non-linear characteristics of subsequent amplifier
stages or of the display. The spectral images are duplicates of the signal spectrum
around multiples of the sampling frequency. These images, a counterpart of aliasing in
the A/D conversion, become visible after D/A conversion. They are only reduced by the
sinx/x characteristic of the D/A converter.
UED10249
0
-50
A
-40
-30
-20
-10
0
10
dB
0.1
0.2
0.3
0.4
0.5
f /
S
f
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| SDA9290-5 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Picture Processor |
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