參數(shù)資料
型號(hào)： SDA5648X
廠商： SIEMENS A G
元件分類： 圖文
英文描述： Decoder for Program Delivery Control and Video Program System PDC / VPS Decoder
中文描述： TELETEXT AND VPS/PDC DECODER, PDSO20
封裝： PLASTIC, DSO-20
文件頁(yè)數(shù)： 6/23頁(yè)
文件大?。?/td> 472K
代理商： SDA5648X
SDA 5648
SDA 5648X
Semiconductor Group
26
I
2
C-Bus
General Information
The
I
2
C-Bus interface implemented on the PDC decoder is a slave transmitter/receiver, i.e., both
reading from and writing to the PDC / VPS decoder is possible. The clock line SCL is controlled only
by the bus master usually being a micro controller, whereas the SDA line is controlled either by the
master or by the slave. A data transfer can only be initiated by the bus master when the bus is free,
i.e., both SDA and SCL lines are in a high state. As a general rule for the
I
2
C-Bus, the SDA line
changes state only when the SCL line is low. The only exception to that rule are the Start Condition
and the Stop Condition. Further details are given below. The following abbreviations are used:
START :
AS :
AM :
NAM :
STOP :
Start Condition generated by master
Ackknowledge by slave
Ackknowledge by master
No Ackknowledge by master
Stop Condition generated by master
Chip Address
There are two pairs of chip addresses, which are selected by the CS0-input pin according to the
following table
Write Mode
For writing to the PDC decoder, the following format has to be used:
Data Transfer (Write Mode)
Step1 In order to start a data transfer the master generates a Start Condition on the bus by pulling
the SDA line low while the SCL line is held high.
Step 2 The bus master puts the chip address on the SDA line during the next eight SCL pulses.
Step 3 The master releases the SDA line during the ninth clock pulse. Thus the slave can generate
an acknowledge (AS) by pulling the SDA line to a low level.
Step 4 The controller transmits the data byte to set the Control register.
Step 5 The slave acknowledges the reception of the byte.
Step 6 The master concludes the data communication by generating a Stop Condition.
The write mode is used to set the
I
2
C-Bus control register which determines the operating mode:
CS0 Input
Write Mode
Read Mode
Low
20 (hex)
21 (hex)
High
22 (hex)
23 (hex)
START
Chipadress White Mode
AS
Byte Set Control Register
AS
STOP
相關(guān)PDF資料
PDF描述
SDA 5648X VPS-Decoder(VPS解碼器)
sda 5648 VPS-Decoder(VPS解碼器)
SDA5649X CAPACITOR, CLASS Y2 56NFCAPACITOR, CLASS Y2 56NF; Capacitance:56nF; Voltage rating, AC:250V; Voltage rating, DC:2500V; Capacitor dielectric type:Polypropylene; Series:B81122; Tolerance, +:20%; Tolerance, -:20%; Temp, op.
SDA5649 Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder
sda 5649x VPS-Decoder(VPS解碼器)
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SDA5649 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder
SDA5649X 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder
SDA5650 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:VPS / PDC-plus Decoder
SDA5650X 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:VPS / PDC-plus Decoder
SDA6000 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Teletext Decoder with Embedded 16-bit Controller
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