參數(shù)資料
型號(hào)： sda5642-6
廠商： SIEMENS AG
英文描述： VPS-Decoder(VPS解碼器)
中文描述： 車輛定位系統(tǒng)解碼器（車輛定位系統(tǒng)解碼器）
文件頁(yè)數(shù)： 11/27頁(yè)
文件大?。?/td> 684K
代理商： SDA5642-6
SDA 5642-6/X
Semiconductor Group
11
02.97
2.2.4
For reading from the VPS decoder, the following format has to be used
Read Mode
:
The contents of up to 16 registers (bytes) can be read starting with byte 1 bit 7 (refer to
the table
Order of Data Output on the
I
2
C Bus and...
) depending on the selected
operating mode.
Description of Data Transfer (Read Mode)
Step1:
To start a data transfer the master generates a Start Condition on the bus by
pulling the SDA line low while the SCL line is held high. The byte address
counter in the decoder is reset and points to the first byte to be output.
Step 2:
The bus master puts the chip address on the SDA line during the next eight
SCL pulses.
Step 3:
The master releases the SDA line during the ninth clock pulse. Thus the slave
can generate an acknowledge (AS) by pulling the SDA line to a low level. At
this moment, the slave switches to transmitting mode.
Step 4:
During the next eight clock pulses the slave puts the addressed data byte
onto the SDA line.
Step 5:
The reception of the byte is acknowledged by the master device which, in
turn, pulls down the SDA line during the next SCL clock pulse. By
acknowledging a byte, the master prompts the slave to increment its internal
address counter and to provide the output of the next data byte.
Step 6:
Steps no. 4 and no. 5 are repeated, until the desired amount of bytes have
been read.
Step 7:
The last byte is output by the slave since it will not be acknowledged by the
master.
Step 8:
To conclude the read operation, the master doesn’t acknowledge the last byte
to be received. A No Acknowledge by the master (NAM) causes the slave to
switch from transmitting to receiving mode. Note that the master can
prematurely cease any reading operation by not acknowledging a byte.
Step 9:
The master gains control over the SDA line and concludes the data transfer
by generating a Stop Condition on the bus, i. e., by producing a low/high
transition on the SDA line while the SCL line is in a high state. With the SDA
and the SCL lines being both in a high state, the
I
2
C Bus is free and ready for
another data transfer to be started.
Start
Chipaddress Read Mode
AS
1st Byte
AM .....
Last Byte
NAM Stop
相關(guān)PDF資料
PDF描述
SDA5648 Decoder for Program Delivery Control and Video Program System PDC / VPS Decoder
SDA5648X Decoder for Program Delivery Control and Video Program System PDC / VPS Decoder
SDA 5648X VPS-Decoder(VPS解碼器)
sda 5648 VPS-Decoder(VPS解碼器)
SDA5649X CAPACITOR, CLASS Y2 56NFCAPACITOR, CLASS Y2 56NF; Capacitance:56nF; Voltage rating, AC:250V; Voltage rating, DC:2500V; Capacitor dielectric type:Polypropylene; Series:B81122; Tolerance, +:20%; Tolerance, -:20%; Temp, op.
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SDA5642-6X 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:VPS-Decoder
SDA5648 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Decoder for Program Delivery Control and Video Program System PDC / VPS Decoder
SDA5648X 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Decoder for Program Delivery Control and Video Program System PDC / VPS Decoder
SDA5649 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder
SDA5649X 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Expanded Decoder for Program Delivery Control and Video Program System EPDC / VPS Decoder
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