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參數(shù)資料
| 型號： | SDA3302-5X6 |
| 廠商： | SIEMENS A G |
| 元件分類： | XO, clock |
| 英文描述： | GHz PLL with I2C Bus and Four Chip Addresses |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 1300 MHz, PDSO16 |
| 文件頁數(shù)： | 24/27頁 |
| 文件大?。?/td> | 864K |
| 代理商： | SDA3302-5X6 |
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Semiconductor Group
24
Application Circuit
Calculation of Loop Filter
Loop bandwidth
ω
R
=
√
(
I
p
×
K
VCO
) / (
C
1
×
P
×
N
)
ξ
= 0.5
×
ω
R
×
R
×
C
1
P
= prescaler
N
= programmable divider
I
p
= pump current
K
VCO
= tuner slope
R
,
C
1
= loop filter
Attenuation:
Example for channel 47:
P
= 8,
N
= 11520,
I
p
= 100
μ
A;
K
VCO
= 18.7 MHz/V,
R
= 22 k
,
C
1
= 180 nF,
ω
R
= 336 Hz,
f
r
= 54 Hz,
ξ
= 0.67
Standard dimensioning:
C
2
=
C
1/5
Note:
The high-impedance port outputs and CAS can be blocked against external noise with
a capacitor of 1 nF.
SDA 3302 Family
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