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Infineon Technologies AG 1999
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Published by Infineon Technologies AG
SDA 9488X Block Diagram
The SDA 9488X integrates different functional blocks on a single chip
I
Input video switch
I
Signal clamping and 8-Bit
AD Converter
I
NTSC, PAL, SECAM Chroma
decoder
I
Decimation logic
I
368 Kbit on-chip memory
Availability
Samples of the SDA 9488X are available for evaluation with complete
documentation. Our highly experienced engineering support team, as
well as our worldwide FAE network can assist you with your design in
work. Please contact your local Infineon office for further details.
Ask for PIP
IV
driver software to simplify your development work.
SDA 9488X Application Example
I
Output signal processing, e.g.
peaking
I
Digital data slicer
I
Triple 7-Bit DA Converter
I
RGB/YUV Switch
I
SYNC processing/generation
and memory control logic
RGB
Matrix
DAC
3x7 Bit
7
7
7
Ι
2
C
Receiver
RGB
Switch
V
DDA 1
V
SSA 1
V
DDA 2
V
DD
V
SS
V
SSA 2
R/V
G/Y
B/U
R/V
G/Y
B/U
BLK
SEL
HSP
VSP
SCL SDA
XIN
XQ
V
REFH
CVBS1*
CVBS2/Y*
CVBS3/C*
Parent
Clock
Synthesizer
V
REF
IRQ
Analog Functions
Digital Functions
Y-Peaking
Frame
Insertion
M
U
X
D
E
Display
Control
Parent
Sync
Processing
DI
PIP
Memory
DO
eDRAM
368 Kbit
Memory
Controller
64
ADR
H/V LP &
Decimation
Skewcomp.
64
64
U
X
M
Insert
Synchron.
PLL
Multi-
standard
Decoder
SYNC
UV
8
8
Y
Y/C & Sync
Separation
CHR8
Input
Switch
Clamp
8 Bit
ADC
Gain
Data
Slicer
DCVBC
8
XO
CLK20
XTAL
20.25 MHz
V
REFL
SDA 9488X
* On the SDA 9588X version the three input pins may alternatively be used for a YUV input signal
Tuner 1
Tuner 2
CVBS 1*
PIP IV Basic
SDA 9488X
G/Y
B/U
R/V
Teletext or
OSD Processor
(optional)
R/V G/Y B/U
BLK
HSYNK
VSYNC
RGB
Processor
R
G
B
R/V
G/Y
B/U
Color Decoder
for Main Channel
CVBS
*The three input pins of the SDA 9488X may also be used for a Y/C and one CVBS signal
or on the SDA 9588X version for a YUV signal
CVBS 2*
(e.g. VCR)
CVBS 3*
(e.g. SAT)
Select
Ordering No. B111-H7499-X-X-7600
Printed in Germany
PS 08993.