參數(shù)資料
型號: sda 9206
廠商: SIEMENS AG
英文描述: ADC with Built in Antialiasing Filter and Clock Generation Unit(帶有片內去混疊和時鐘發(fā)生器的A/D轉換器)
中文描述: 在抗混疊濾波器和時鐘產(chǎn)生單元內置模數(shù)轉換器(帶有片內去混疊和時鐘發(fā)生器的的A / D轉換器)
文件頁數(shù): 11/54頁
文件大小: 530K
代理商: SDA 9206
SDA 9206
Semiconductor Group
11
1999-02-10
1.4
Pin Description
(cont’d)
S: supply,
ana: analog,
I: input,
pu: internal pullup-circuit,
Q: output,
TTL: digital (TTL)
pd: internal pulldown-circuit
1.5
Internal Pin Configuration
Figure 2
Figure 3
Pin No.
63
64
Symbol
V
REFHC
V
ADDC
Type
Description
Reference voltage high of ADC SYNC (4.2 V)
Analog positive supply voltage of ADC SYNC (5 V)
UES10549
PAD
Pin 2, 4, 7, 9, 12, 14, 61, 63
V
REFHY
,
V
V
,
REFLY
V
REFHU
V
,
REFLU
,V
REFHV
V
,
V
,
REFLV
REFLC
REFHC
,
UES10550
PAD
Pin 17, 18, 19, 20, 24...31, 37...44, 51, 52, 53, 54
H1I1, RESOUTN, BLN, H2I2, PAQ7...0, PBQ7...0, VS, CLK2,
CLK1, HS
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