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參數(shù)資料
| 型號： | sda 9188 |
| 廠商： | SIEMENS AG |
| 英文描述： | Picture-in-Picture Processor with On-Chip PLL(片內(nèi)鎖有相環(huán)的畫中畫處理器) |
| 中文描述： | 子母畫面處理器的片上鎖相環(huán)（片內(nèi)鎖有相環(huán)的畫中畫處理器） |
| 文件頁數(shù)： | 2/31頁 |
| 文件大?。?/td> | 450K |
| 代理商： | SDA 9188 |
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Semiconductor Group
2
The PIP processor SDA 9188-3X handles picture reduction (decimation with horizontally and
vertically acting filters), intermediate data storage in an integrated image memory (169.812 bits) as
well as the output of the decimated picture.
The picture can be set 1/9 or 1/16 of its original size. In order to indicate the border between parent
picture and inset picture the inset picture can be surrounded with a frame: its width is adjustable in
2 stages and its brightness in 16 stages. Different signal sources can be identified by using different
framing colors. The four corners of the parent picture are possible positions for the inset picture. The
inset picture can also be inserted as a still picture, independently of the parent picture.
The output signals of the SDA 9188-3X are analog. Either RGB or Y, U, V signals can be output,
whereby a 6-bit broadband conversion is obtained for all components. Clamping for RGB output
signal is performed in an RGB processor (e.g. TDA 4685).
Only a few additional devices are required for a complete picture-in-picture system.
Application
circuits 1a and 1b
illustrate the use of the PIP device.
If the CVBS input signal is to be decoded using an analog color decoder for the PIP, the analog/
digital interface for the inset picture (3 A/D Converter, SDA 9187-2X) performs the conversion of the
Y, U, V components into digital signals as well as the generation of the inset clocks BLNI and LL3I.
The SDA 9188-3X processes both 50 Hz/625 and 60 Hz/525 line signals. The field frequency can
be 50/60 Hz or 100/120 Hz. For systems with Siemens Dig TV Featurebox a field frequency of 100
Hz or 120 Hz is also possible by doubling the clock frequency LL3P (LL1.5P). Frame mode display
with 50 Hz or 60 Hz can also be set via the
I
2
C bus. Adaptation to the number of lines occurs
automatically. If the field frequency in the parent and inset channels are different, artifacts may
result in the picture.
Synchronization with the parent channel is performed via the horizontal and vertical sync signals
HSP/SAND and VSP. The clock fequency is 13.5 MHz (LL3P) without standard conversion and
27 MHz (LL1.5P) with standard conversion (100/120 Hz). The display clock is generated on chip.
Optionally the external clock generator SDA 9086-3 can be used in the same way as with the
SDA 9188X.
The horizontal and vertical sync signals BLNI and VSI plus the LL3I clock (13.5 MHz) are used for
synchronization with the inset source.
The interface between inset and parent channel is done by the on-chip memory. The memory write
access is controlled by the inset clock and the read access is controlled by the parent clock.
The SELECT output signal inserts the inset picture into the parent picture driving an external analog
switch, e.g. the TDA 4685. All operation modes of the SDA 9188-3X can be controlled via the
I
2
C
bus. Nine registers can be used.
SDA 9188-3X
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SDA9188-3X | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Picture-in-Picture Processor with On-Chip PLL |
| SDA9189 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:畫中畫子畫面處理集成電路 |
| SDA9189X | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Quarter PIP Processor |
| SDA9189X-A132 | 制造商:Siemens 功能描述:Part Number Only |
| SDA9205-2 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Triple 8-Bit Analog-to-Digital-Converter |
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