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    • 參數(shù)資料
      型號: SD-14531D5-295
      廠商: DATA DEVICE CORP
      元件分類: 位置變換器
      英文描述: SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, MDMA36
      封裝: KOVAR, DDIP-36
      文件頁數(shù): 11/16頁
      文件大?。?/td> 170K
      代理商: SD-14531D5-295
      4
      Data Device Corporation
      www.ddc-web.com
      SD-14531
      VALUE
      Notes:
      (1) Pin Programmable.
      (2) VEL polarity is negative voltage for positive angular rate.
      (3) XX5 ordering option = ±1.3 minutes resolver mode, ±1.6 minutes synchro
      mode (16-bit mode only).
      TRANSFORMER
      CHARACTERISTICS (CONT.)
      Minimum Input impedances
      (Balanced)
      90 V L-L
      26 V L-L
      11.8 V L-L
      60 Hz TRANSFORMERS
      Reference Transformer
      Carrier Frequency Range
      Input Voltage Range
      Input Impedance
      Input Common-Mode Voltage
      Output Description
      Output Voltage
      Power Required
      Signal Transformer
      Carrier Frequency Range
      Input Voltage Range
      Input Impedance
      Input Common-Mode Voltage
      Output Description
      Output Voltage
      Power Required
      PARAMETER
      TABLE 1. SD-14531 SPECIFICATIONS (CONT.)
      accuracy of the converter. The control transformer performs the
      following trigonometric computation:
      sin(
      θ - φ) = sinθ cosφ - cosθ sinφ
      Where:
      θ is angle theta representing the resolver shaft position
      φ is digital angle phi contained in the up/down counter
      The tracking process consists of continually adjusting
      φ to make
      (
      θ - φ) = 0, so that φ will represent the shaft position θ.
      The output of the demodulator is an analog DC level proportion-
      al to sin(
      θ - φ). The error processor receives its input from the
      demodulator and integrates this sin(
      θ - φ) error signal which then
      drives the VCO. The VCO’s clock pulses are accumulated by the
      up/down counter. The velocity voltage accuracy, linearity and off-
      set are determined by the quality of the VCO. Functionally, the
      up/down counter is an incremental integrator. Therefore, there
      are two stages of integration which makes the converter a Type
      II tracking servo.
      In a Type II servo, the VCO always settles to a counting rate
      which makes d
      φ/dt equal to dθ/dt without lag. The output data will
      always be fresh and available as long as the maximum tracking
      rate of the converter is not exceeded.
      The reference conditioner is a comparator that produces the
      square wave reference voltage which drives the demodulator. It’s
      single-ended Input Z is 250k Ohms min, 500k Ohms differential.
      SPECIAL FUNCTIONS
      The synthesized reference section of the SD-14531 eliminates
      errors caused by quadrature voltage. Due to the inductive nature
      of synchros and resolvers, their signals typically lead the refer-
      ence signal (RH and RL) by about 6°. When an uncompensated
      reference signal is used to demodulate the control transformer’s
      output, quadrature voltages are not completely eliminated. In a
      14-bit converter it is not necessary to compensate for the refer-
      ence signal’s phase shift. A 6° phase shift will, however, cause
      problems for the one minute accuracy converters. As shown in
      FIGURE 1, the converter synthesizes its own cos(
      ωt + α) refer-
      ence signal from the sin
      θ - cos(ωt + α), cosθ - cos(ωt + α) signal
      inputs and from the cos
      ωt reference input. The phase angle of
      the synthesized reference is determined by the signal input. The
      reference input is used to choose between the +180° and -180°
      phases. The synthesized reference will always be exactly in
      phase with the signal input, and quadrature errors will therefore
      be eliminated. The synthesized reference circuit also eliminates
      the 180° false error null hangup.
      Quadrature voltages in a resolver or synchro are by definition the
      resulting 90° fundamental signal in the nulled out error voltage
      THEORY OF OPERATION
      The SD-14531 Series are small, 36-pin DDIP synchro-to-digital
      hybrid converters. As shown in the block diagram (FIGURE 1),
      the SD-14531 can be broken down into the following functional
      parts: Signal Input Option, Converter, Analog Conditioner, Power
      Supply Conditioner, and Digital Interface.
      CONVERTER OPERATION
      As shown in FIGURE 1, the converter section of the SD-14531
      contains a high accuracy control transformer, demodulator, error
      processor, voltage-controlled oscillator (VCO), up-down counter,
      and reference conditioner. The converter produces a digital
      angle which tracks the analog input angle to within the specified
      SynchroZIN(ZSO)
      ResolverZIN
      180
      100 k
      -
      30 k
      20 k
      30 k
      47 - 440 Hz
      80 -138 V rms; 115 V rms
      nominal resistive
      600 k
      min, resistive
      500 V rms transformer isolated
      +R (in phase with RH-RL) and -R
      (in phase with RL- RH) derived
      from op-amps. Short-Circuit proof.
      3.0 V nominal riding on ground
      reference V. Output Voltage level
      tracks input level.
      4 mA typ, 7 mA max from +15 V
      supply.
      47 - 440 Hz
      10 -100 V rms L- L; 90 V rms
      L- L nominal
      148 k
      min L- L balanced
      resistive
      ±500 V rms, transformer isolated
      Resolver output,
      - Sine (- S) + Cosine (+C) derived
      from op-amps. Short circuit proof.
      1.0 V rms nominal riding on
      ground reference V. Output volt-
      age level tracks input level.
      4 mA typ, 7 mA max from +15 V
      supply.
      相關(guān)PDF資料
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