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參數(shù)資料
| 型號(hào)： | SCS-QL-1124 |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 20 MHz, HCMOS OUTPUT |
| 封裝： | RESISTANCE WELDED, METAL, DIP-4 |
| 文件頁(yè)數(shù)： | 1/2頁(yè) |
| 文件大?。?/td> | 115K |
| 代理商： | SCS-QL-1124 |
SaRonix
SCS-QL-1124, SCS-QL-1125
SaRonix
Crystal Clock Oscillator
Technical Data
3.3V, Tri-State, HCMOS
141 Jefferson Drive Menlo Park, CA 94025 USA 650-470-7700 800-227-8974 Fax 650-462-9894
DS-159 REV CS R0085
20.0000 MHz = SCS-QL-1124
25.0000 MHz = SCS-QL-1125
Frequency Stability:
Frequency Range:
±100 ppm over all conditions: calibration tolerance,
operating temperature, input voltage change, load
change, 30 day aging, shock and vibration.
Temperature Range:
Operating:
Storage:
0 to +70°C
-55 to +125°C
Supply Voltage:
Recommended Operating:
3.3V ±10%
Supply Current:
15mA max
ACTUAL SIZE
Description
A crystal controlled, low current, low
jitter oscillator with precise rise and fall
times demanded in networking applica-
tions, such as Gigabit Ethernet and Fibre
Channel. The tri-state function enables the
output to go high impedance. Device is
packaged in an 8-pin DIP compatible resis-
tance welded, all metal grounded case, to
reduce EMI.
Output Drive:
Symmetry:
Rise and Fall Times:
Logic 0:
Logic 1:
Load:
Period Jitter RMS:
40/60% max @ 50% V
DD
4ns max 20% to 80% V
DD
10% V
DD
max
90% V
DD
min
30 pF, 1 to 80 MHz
8ps max
HCMOS
Mechanical:
Shock:
Solderability:
Terminal Strength:
Vibration:
Solvent Resistance:
Resistance to Soldering Heat:
MIL-STD-883, Method 2002, Condition B
MIL-STD-883, Method 2003
MIL-STD-202, Method 211, Conditions A & C
MIL-STD-883, Method 2007, Condition A
MIL-STD-202, Method 215
MIL-STD-202, Method 210, Condition A, B or C
Environmental:
Gross Leak Test:
Fine Leak Test:
Thermal Shock:
Moisture Resistance:
MIL-STD-883, Method 1014, Condition C
MIL-STD-883, Method 1014, Condition A2
MIL-STD-883, Method 1011, Condition A
MIL-STD-883, Method 1004
Applications & Features
Fibre Channel
Tri-State output
HCMOS compatible
3.3Volt operation
Output Waveform
T
r
T
f
CMOS
Logic 1
80% V
DD
50% V
DD
20% V
DD
Logic 0
SYMMETRY
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