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| 型號(hào)： | SCN2661BC1N28 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | SM Series Subminiature Basic Switch, Single Pole Double Throw (SPDT), 250 Vac, 5 A, Pin Plunger Actuator, Solder Termination |
| 中文描述： | 1 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁(yè)數(shù)： | 12/19頁(yè) |
| 文件大?。?/td> | 131K |
| 代理商： | SCN2661BC1N28 |
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Philips Semiconductors
Product specification
SCN2661/SCN68661
Enhanced programmable communications
interface (EPCI)
1994 Apr 27
12
1. The transmitter output is connected to the receiver input.
2. DTR is connected to DCD and RTS is connected to CTS.
3. The receiver is clocked by the transmit clock.
4. The DTR, RTS and TxD outputs are held High.
5. The CTS, DCD, DSR and RxD inputs are ignored.
Additional requirements to operate in the local loopback mode are
that CR0 (TxEN), CR1 (DTR) and CR5 (RTS) must be set to 1.
CR2 (RxEN) is ignored by the EPCI.
The second diagnostic mode is the remote loopback mode (CR7 –
CR6 = 11). In this mode:
1. Data assembled by the receiver are automatically placed in the
transmit holding register and retransmitted by the transmitter on
the TxD output.
2. The transmitter is clocked by the receiver clock.
3. No data are sent to the local CPU, but he error status conditions
(PE, FE) are set.
4. The RxRDY, TxRDY, and TxEMT/DSCHG outputs are held High.
5. CR0 (TxEN) is ignored.
6. All other signals operate normally.
Status Register
The data contained in the status register (as shown in Table 8)
indicates receiver and transmitter conditions and modem/data set
status.
SR0 is the transmitter ready (TxRDY) status bit. It, and its
corresponding output, are valid only when the transmitter is enabled.
If equal to 0–, it indicates that the transmit data holding register has
been loaded by the CPU and the data has not been transferred to
the transmit register. If set equal to 1, it indicates that the holding
register is ready to accept data from the CPU. This bit is initially set
when the transmitter is enabled by CR0, unless a character has
previously been loaded into the holding register. It is not set when
the automatic echo or remote loopback modes are programmed.
When this bit is set, the TxRDY output pin is Low. In the automatic
echo and remote loopback modes, the output is held High.
SR1, the receiver ready (RxRDY) status bit, indicates the condition
of the receive data holding register. If set, it indicates that a
character has been loaded into the holding register from the receive
shift register and is ready to be read by the CPU. If equal to zero,
there is no new character in the holding register. This bit is cleared
when the CPU reads the receive data holding register or when the
receiver is disabled by CR2. When set, the RxRDY output is Low.
The TxEMT/DSCHG bit, SR2, when set, indicates either a change of
state of the DSR or DCD inputs (when CR2 or CR0 = 1) or that the
transmit shift register has completed transmission of a character and
no new character has been loaded into the transmit data holding
register. Note that in synchronous mode this bit will be set even
though the appropriate “fill” character is transmitted. TxEMT will not
go active until at least one character has been transmitted. It is
cleared by loading the transmit data holding register. The DSCHG
conditions is enabled when TxEN = 1 or RxEN = 1. It is cleared
when the status register is read by the CPU. If the status register is
read twice and SR2 – 1 while SR6 and SR7 remain unchanged,
then a TxEMT condition exists. When SR2 is set, the
TxEMT/DSCHG output is Low.
SR3, when set, indicates a received parity error when parity is
enabled by MR14. In synchronous transparent mode (MR16 = 1),
with parity disabled, it indicates that a character matching DLE
register was received and the present character is neither SYN2 or
DLE. This bit is cleared when the next character following the
above sequence is loaded into RHR, when the receiver is disabled,
or by a reset error command, CR4.
The overrun error status bit, SR4, indicates that the previous
character loaded into the receive holding register was not ready the
CPU at the time of new received character was transferred into it.
This bit is cleared when the receiver is disabled or by the reset error
command, CR4.
In asynchronous mode, bit SR5 signifies that the received character
was not framed by a stop bit; i.e., only the first stop bit is checked. If
RHR = 0 when SR5 = 1, a break condition is present. In
synchronous non-transparent mode (MR16 = 0), it indicates receipt
of the SYN1 character in single SYN mode or the SYN1 – SYN2 pair
in double SYN mode. In synchronous transparent mode (MR16 =
1), this bit is set upon detection of the initial synchronizing
characters (SYN or SYN1 – SYN2) and, after synchronization has
been achieved, when a DLE–SYN1 pair is received. The bit is reset
when the receiver is disabled, when the reset error command is
given in asynchronous mode, or when the status register is read by
the CPU in the synchronous mode.
SR6 and SR7 reflect the conditions of the DCD and DSR inputs,
respectively. A Low input sets its corresponding status bit, and a
High input clears it.
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PDF描述 |
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| SCN2661CA1F28 | SM Series Subminiature Basic Switch, Single Pole Double Throw (SPDT), 250 Vac, 5 A, Pin Plunger Actuator, Solder Termination |
| SCN2661CC1A28 | Enhanced programmable communications interface EPCI |
| SCN2661CC1F28 | SM Series Subminiature Basic Switch, Single Pole Double Throw (SPDT), 125 Vac, 1 A, Pin Plunger Actuator, Solder Termination |
| SCN2661CC1N28 | Enhanced programmable communications interface EPCI |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCN2661CA1F28 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced programmable communications interface EPCI |
| SCN2661CC1A28 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced programmable communications interface EPCI |
| SCN2661CC1F28 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced programmable communications interface EPCI |
| SCN2661CC1N28 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced programmable communications interface EPCI |
| SCN2672AC4N40 | 制造商:North American Philips Discrete Products Div 功能描述:NON-VGA VIDEO CONTROLLER, 40 Pin, DIP |
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