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參數(shù)資料
| 型號： | SCM69C233 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4K x 64 Content Addressable Memory(4K x 64內(nèi)容可尋址存儲器) |
| 中文描述： | 4K的× 64內(nèi)容可尋址存儲器（4K的× 64內(nèi)容可尋址存儲器） |
| 文件頁數(shù)： | 5/22頁 |
| 文件大?。?/td> | 167K |
| 代理商： | SCM69C233 |
MCM69C233
SCM69C233
5
MOTOROLA FAST SRAM
CAPACITANCE
(Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Min
Max
Unit
Input Capacitance
Cin
CI/O
—
5
pF
I/O Capacitance
—
8
pF
JUNCTION TO AMBIENT THERMAL CHARACTERISTICS
Board
Air (LFPM)
θ
JA (
°
C/W)
40.1
Maximum Ambient Temperature (
°
C)
1 Layer
0
55.8
1 Layer
200
34.7
64.4
1 Layer
400
32.1
68.7
4 Layer
0
30.5
71.1
4 Layer
200
27.1
76.6
4 Layer
400
25.6
79.0
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V
±
5%, TJ < 120
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
3 ns
Output Timing Reference Level
Output Load
. . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 1 Unless Otherwise Noted
CONTROL PORT TIMINGS
(Voltages Referenced to VSS = 0 V, Max’s are tKHKH Dependent and Listed Values are for tKHKH = 15 ns)
Parameter
Symbol
Min
Max
Unit
Notes
Address Valid to SEL Low
tAVSL
0
—
ns
DTACK Low to Address Invalid
tDTLAX
0
—
ns
Data Valid to Select Low
tDVSL
0
—
ns
DTACK Low to Data Invalid
tDTLDX
0
—
ns
Output Valid to DTACK Low
tQVDTL
2
—
ns
WE Valid to Select Low
tWVSL
0
—
ns
DTACK Low to WE High
tDTLWH
0
—
ns
WE High to Output Active
tWHQX
2
—
ns
Select Low to DTACK Low
tSLDTL
10
—
ns
1
Select High to DTACK High
tSHDTH
10
20
ns
DTACK Low to IRQ Low
tDTLIL
10
—
ns
IRQ Low to IRQ High
tILIH
20
—
ns
DTACK Low to Select High
tDTLSH
0
—
ns
DTACK High to Select Low
tDTHSL
0
—
ns
Address Valid to Output Valid
tAVQV
—
8
ns
Select High to Output High Impedance
tSHQZ
—
8
ns
RESET Low to RESET High
tRLRH
2 x tKHKH
—
ns
NOTE:
1. DTACK is delayed when a write is attempted during certain operations. See Functional Description.
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