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參數(shù)資料
| 型號(hào)： | SCF5742 |
| 廠商： | SIEMENS A G |
| 元件分類： | 顯示用LED |
| 英文描述： | 0.270” 4-Character, 5x7 Dot Matrix Serial Input Dot Addressable Intelligent Display |
| 中文描述： | 5X7 DOT MATRIX DISPLAY, HIGH EFFICIENCY RED, 6.86 mm |
| 封裝： | PLASTIC, DIP-22 |
| 文件頁(yè)數(shù)： | 2/12頁(yè) |
| 文件大?。?/td> | 93K |
| 代理商： | SCF5742 |
2–201
SCF5740/2/4
Maximum Rating
DC Supply Voltage ........................................–0.5 to +7.0 Vdc
Input Voltage Levels Relative
to Ground................................................–0.5 toV
Operating Temperature ................................. –40
Storage Temperature.................................... –40
Maximum Solder Temperature 0.063"
below Seating Plane, t<5 sec...................................... 260
Relative Humidity at 85
°
C................................................. 85%
Maximum Number of LEDs at 100% Brightness ................. 64
Maximum Power Dissipation ........................................ 0.65 W
ESD (100 pF, 1.5 K
)........................................................2 KV
Maximum Input Current.............................................
CC
°
C to +85
C to +100
+0.5 Vdc
°
°
C
C
°
°
C
±
186 mA
Switching Specifications
(over operating temperature range and V
CC
=4.5 V to 5.5 V)
Symbol
Description
Min.
Units
T
RC
Reset Active Time
600
ns
T
LDS
Load Setup Time
50
ns
T
DS
Data Setup Time
50
ns
T
SDCLK
Clock Period
200
ns
T
SDCW
Clock Width
70
ns
T
LDH
Load Hold Time
0
ns
T
DH
Data Hold Time
25
ns
T
WR
Total Write Time
2.2
μ
s
T
BL
Time Between Loads
600
ns
Note:
TSDCW is the minimum time the SDCLK may be low or high. The
SDCLK period must be a minimum of 200 ns.
Figure 1. Timing diagram–Data write cycle
Figure 2. Timing diagram–Instruction cycle
SDCLK
SDCLK
T
SDCW
T
DATA
LOAD
D0
DS
T
LDS
T
TDH
D7
LDH
T
LOAD
LOAD
DATA
DATA
SDCLK
SDCLK
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
D0
D0
BL
T
WR
T
OR
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