參數(shù)資料
型號(hào)： SCC2681AC1N40,112
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 3/29頁(yè)
文件大小： 0K
描述： IC UART DUAL 40-DIP
產(chǎn)品培訓(xùn)模塊： Stand-Alone UARTs
標(biāo)準(zhǔn)包裝： 9
特點(diǎn)： 故障啟動(dòng)位檢測(cè)
通道數(shù)： 2，DUART
FIFO's： 3 位
電源電壓： 5V
帶并行端口： 是
帶自動(dòng)流量控制功能： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶CMOS： 是
安裝類型： 通孔
封裝/外殼： 40-DIP（0.600"，15.24mm）
供應(yīng)商設(shè)備封裝： 40-DIP
包裝： 管件
其它名稱： 568-3525-5
935274523112
SCC2681AC1N40
Philips Semiconductors
Product data
SCC2681
Dual asynchronous receiver/transmitter (DUART)
2004 Apr 06
11
PROGRAMMING
The operation of the DUART is programmed by writing control words
into the appropriate registers. Operational feedback is provided via
status registers which can be read by the CPU. The addressing of
the registers is described in Table 1.
The contents of certain control registers are initialized to zero on
RESET. Care should be exercised if the contents of a register are
changed during operation, since certain changes may cause
operational problems.
For example, changing the number of bits per character while the
transmitter is active may cause the transmission of an incorrect
character. In general, the contents of the MR, the CSR, and the
OPCR should only be changed while the receiver(s) and
transmitter(s) are not enabled, and certain changes to the ACR
should only be made while the C/T is stopped.
Mode registers 1 and 2 of each channel are accessed via
independent auxiliary pointers. The pointer is set to MR1x by
RESET or by issuing a ‘reset pointer’ command via the
corresponding command register. Any read or write of the mode
register while the pointer is at MR1x, switches the pointer to MR2x.
The pointer then remains at MR2x, so that subsequent accesses are
always to MR2x unless the pointer is reset to MR1x as described
above.
Mode, command, clock select, and status registers are duplicated
for each channel to provide total independent operation and control.
Refer to Table 2 for register bit descriptions.
Table 1.
SCC2681 Register Addressing
A3
A2
A1
A0
READ (RDN = 0)
WRITE (WRN = 0)
0
Mode Register A (MR1A, MR2A)
0
1
Status Register A (SRA)
Clock Select Register A (CSRA)
0
1
0
BRG Extend *
Command Register A (CRA)
0
1
Rx Holding Register A (RHRA)
Tx Holding Register A (THRA)
0
1
0
Input Port Change Register (IPCR)
Aux. Control Register (ACR)
0
1
0
1
Interrupt Status Register (ISR)
Interrupt Mask Register (IMR)
0
1
0
Counter/Timer Upper Value (CTU)
C/T Upper Preset Value (CRUR)
0
1
Counter/Timer Lower Value (CTL)
C/T Lower Preset Value (CTLR)
1
0
Mode Register B (MR1B, MR2B)
1
0
1
Status Register B (SRB)
Clock Select Register B (CSRB)
1
0
1
0
1
×/16× Test
Command Register B (CRB)
1
0
1
Rx Holding Register B (RHRB)
Tx Holding Register B (THRB)
1
0
Use for scratch pad
1
0
1
Input Ports IP0 to IP6
Output Port Conf. Register (OPCR)
1
0
Start Counter Command
Set Output Port Bits Command
1
Stop Counter Command
Reset Output Port Bits Command
* See Table 5 for BRG Extended frequencies in this data sheet, and
“Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692,
SCC68692 and SCC2698B” in application notes elsewhere in this publication.
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