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參數(shù)資料
| 型號： | SCANSTA111 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port |
| 中文描述： | 增強掃描橋梁多點尋址的IEEE 1149.1（JTAG接口）端口 |
| 文件頁數(shù)： | 22/29頁 |
| 文件大?。?/td> | 524K |
| 代理商： | SCANSTA111 |
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Special Features
(Continued)
registers (one register per LSP). The GPIO outouts are
updated during the
UPDATE-DR
state and the GPIO input
values are written to the corresponding GPIO register during
the
CAPTURE-DR
state.
LSP SHARED:
In the shared mode of opeartion, the dot1
LSP pins TDI
, TDO
and TMS
n
pins become GPIO pins.
TMS
n
and TDO
n
are outputs, TDI
n
is an input in the GPIO
mode.
The sequence of operations to use shared GPIOs on an LSP
are as follows (example uses LSP
0
):
1.
IR-Scan the STA111 address into the instruction register
(address a STA111).
2.
IR-Scan the
MODESEL
instruction into the instruction
register to select Mode Register
(Shared GPIO configu-
ration register) as the data register.
3.
DR-Scan 00000001 into Mode Register
to enable
GPIOs on LSP
. The GPIOs will be enabled when the
TAP enters the
RTI
state at the end of this shift operation
(TDO
and TMS
will be forced to logic 0 as defined by
the default value in the Shared GPIO Register
0
).
4.
IR-Scan the
SGPIO
instruction into the instruction reg-
ister to select the Shared GPIO Register
0
as the data
register.
5.
DR-Scan 00000011 into the Shared GPIO Register
0
to
set TDO
0
and TMS
0
to a logic 1 (when TAP enters
Update-DR
). During this operation, when the TAP enters
Capture-DR
, the present value on the TDI
0
pin and the
values of TDO
0
and TMS
0
(as set by Shared GPIO
Register
0
) will be captured into bits 2, 1 and 0 of the shift
register and will be scanned out 00000X00 (X = value
present on TDI
0
when TAP enters
Capture-DR
).
6.
Step 5 can be repeated to generate waveforms on TDO
0
and TMS
0
. If step 5 was repeated with 00000000 as
data, TDO
and TMS
would be set to a logic 0 (when
TAP state =
Update-DR
) and 00000X11 would be
scanned out (X = value present on TDI
0
when TAP
enters
Capture-DR
).
7.
IR-Scan the
GOTOWAIT
or
SOFTRESET
instruction, or
generate a TRST
B
reset to disable the GPIOs.
ADDRESS INTERROGATION
The STA111 has four states that it can goto from the
Wait-
For-Address
state:
Unselected
,
Singularly-selected
,
Multi/
Broadcast-selected
, and
Address-interrogation
(see
Figure
13
).
After a reset (or
GOTOWAIT
command) has been issued,
the STA111 TAP is sequenced to the
Capture-IR
state where
XXXXXX01 is loaded into the shift register. Upon entering
the
Shift-IR
state, the instruction register is filled with the
address interrogation value (3A hex) which is loaded into the
address register as the TAP is sequenced into the
Update-IR
state. On the next loop through
Capture-IR
the shift register
is loaded with the ones-complement of the slot address. In
the
Shift-IR
state the address interrogation value is loaded
into the instruction register. The value presented on TDO
B
will be a wired-and address of all of the STA111s on the bus.
As this value is being shifted out, each STA111 will monitor
its TDO
to see if it is receiving the same value it is driving.
If the device shifts all bits of its ones-complement address
and never gets a compare error it will tri-state TDO
and go
to the
Wait-For-Reset
state. Alternately, if the device sees a
compare error while it is shifting its ones-complement ad-
dress it will stop shifting its address and tri-state TDO
B
until
the next shift operation; during the next
Shift-IR
operation it
will again try to present its address (if the previous instruction
was 3A hex) while monitoring TDO
B
.
Shifting 3A hex into the instruction registers of the STA111s
will continue until all STA111s have presented their address.
At this time all devices will be waiting to be reset, and if a 3A
is shifted into the STA111 instruction registers the address
read by the tester will be all weak 1s due to all TDO
B
’s being
tri-stated. Reading all ones will signal the tester that address
interrogation is complete. Since all ones signifies the end of
Address-Interrogation
, no device can have an address of all
zeros (ones-complement).
If at any time, during the address interrogation mode, any
other instruction besides 3A hex is shifted into the instruction
register, then the STA111 will exit the interrogation mode.
Also, the STA111’s state machine will go to the
Wait-For-
Address
state.
This address interrogation scheme presumes that TDO
is
capable of driving a weak 1 and that an STA111 driving a 0
will overdrive an STA111 driving a weak 1.
The following is an example of the
Address-Interrogation
function. Assume there are three STA111s (U1, U2 and U3)
on a dot1 backplane with slot addresses 010100, 100000
and 000001 respectively (assuming 6 address pins).
1.
The STA111s are reset and the interrogation address/
op-code (3A hex) is shifted into the instruction registers.
2.
At the end of the instruction shift (
Update-IR
) the STA111
address registers are loaded with 3A hex.
3.
The TAPs are sequenced to
Capture-IR
and the shift
registers latch the ones-complement slot addresses
(U1=101011, U2=011111 and U3=111110).
4.
The TAPs are sequenced to
Shift-IR
and the LSB of the
interrogation address is presented on the TDI
B
’s. Con-
currently, the LSBs of the ones-complement slot ad-
dresses are presented on the respective TDO
B
’s.
5.
The weak 1 being driven on U1 and U2 is overdriven by
the 0 from U3. U1 and U2 enter the
Wait-For-Next-
Interrogation
state.
6.
The shift operation continues and U3 finishes shifting its
ones-complement address (111110) out on TDO
. U3
enters the
Wait-For-Reset
state when the TAP enters
Update-IR
.
7.
The TAPs are again sequenced to
Capture-IR
and U1
and U2 shift registers latch the ones-complement ad-
dresses (U1=101011, U2=011111).
8.
The TAPs are sequenced to
Shift-IR
and the LSB of the
interrogation address is presented on the TDI
’s. Con-
currently, the LSBs of the ones-complement addresses
are presented on the respective TDO
B
’s.
9.
Since both U1 and U2 are driving a weak 1 the shift
continues.
10. Again U1 and U2 drive weak 1 and the shift continues.
11. U2s weak 1 is overdriven by U1s 0 and U2 enters the
Wait-For-Next-Interrogation
state.
12. The shift operation continues and U1 finishes shifting its
ones-complement address (101011) out on TDO
B
. U1
enters the
Wait-For-Reset
state.
13. The instruction shift operation is repeated and U2 shifts
its ones-complement address (011111) out on TDO
B
. U2
enters the
Wait-For-Reset
state.
S
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| SCANSTA111_05 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Enhanced SCAN bridge Multidrop Addressable IEEE 1149.1 (JTAG) Port |
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| SCANSTA111MT/NOPB | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
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| SCANSTA111MTX | 功能描述:接口 - 專用 RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
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