參數(shù)資料
型號(hào)： SCANPSC100FSC
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 微控制器/微處理器
英文描述： Embedded Boundary Scan Controller (IEEE 1149.1 Support)
中文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PDSO28
封裝： 0.300 INCH, MS-013, SOIC-28
文件頁(yè)數(shù)： 7/21頁(yè)
文件大小： 208K
代理商： SCANPSC100FSC
7
www.fairchildsemi.com
S
Parallel Processor Interface (PPI)
(Continued)
TIMING WAVEFORMS (Continued)
FIGURE 4. Consecutive Read/Writes (best case timing)
FIGURE 5. Consecutive Read/Writes (worst case timing)
Note 3: Figures 4, 5:
Figure 4 shows the best case bus cycle timing for SCK and STB during consecutive read or write cycles. The rising edge of strobe
occurs a setup time, t
S4
or before the falling edge of SCK. This allows the cycle to be completed within 1.5 clock SCK clock cycles. Figure 5 shows the worst
case bus cycle timing for SCK and STB during consecutive read or write cycles. The rising edge of strobe does not meet the t
S4
requirement between STB
and SCK. Therefore, the propagation of the internal PSC100 control and reset signals is delayed until the next falling edge of SCK. The bus cycle is then
completed 1.5 SCK cycles later creating a total bus cycle time of 2.5 SCK cycles. If worst case timing is considered for bus cycle timing, t
S4
is not a manda-
tory timing specification.
FIGURE 6. Read/Write or Write/Read (best case timing)
FIGURE 7. Read/Write or Write/Read (worst case timing)
Note 4:
Figures 6, 7: This diagram shows the timing for a read followed by a write (or write followed by a read). Separate Read and Write data/address
latches and control logic allow consecutive read/write or write/read operations to be overlapped (i.e., do not need to wait 2 or 3 SCK cycles between bus
cycles). For the best case timing scenario (Figure 6: rising edge of STB to falling edge of SCK greater than t
S4
), a new bus cycle can be performed each SCK
cycle. For the worst timing scenario (Figure 7: rising edge of STB to falling edge of SCK is less than t
S4
), a one SCK cycle delay must be included after each
back to back read/write or write/read sequence.
Note 5:
Figures 4, 5, 6, 7 assume that the PSC100 register participating in the bus cycle is ready to accept/provide data. For bus cycles involving a PSC100
shifter/buffer(s), the ready status of a shifter/buffer can be checked using the status bits in Mode Register 2 prior to the start of the bus cycle. Polling is
required when the RDY pin is not used to provide a processor
“
handshake
”
.
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