- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376340 > SCAN926260 (National Semiconductor Corporation) Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST PDF資料下載
參數(shù)資料
| 型號： | SCAN926260 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
| 中文描述： | 六1至10巴士符合IEEE 1149.1和在速度BIST的LVDS解串器 |
| 文件頁數(shù)： | 11/18頁 |
| 文件大小： | 372K |
| 代理商： | SCAN926260 |
IEEE 1149.1 Test Modes
The SCAN926260 features interconnect test access that is
compliant to the IEEE 1149.1 Standard for Boundary Scan
Test (JTAG).All digital TTL I/O’s on the device are accessible
using IEEE 1149.1, and entering this test mode will override
all input control cases including power down and REN. In
addition to the four required Test Access Port (TAP) signals
of TMS, TCK, TDI, and TDO, TRST is provided for test reset.
To supplement the test coverage provided by the IEEE
1149.1 test access to the digital TTL pins, the SCAN926260
has two instructions to test the LVDS interconnects. The first
is EXTEST. This is implemented at LVDS levels and is only
intended as a go no-go test (e.g. missing cables). The sec-
ond method is the RUNBIST instruction. It is an "at-system-
speed" interconnect test. It is executed in approximately
33ms with a system clock speed of 66MHz. There are 12 bits
in the RX BIST data register for notification of PASS/FAIL
and TEST_COMPLETE, with two bits for each of the six
channels. The RX BIST register is defined as (from MSB to
LSB):
RX BIST Register
Bit Number
11 (MSB)
10
9
8
7
6
5
4
3
2
1
0 (LSB)
Description
BIST COMPLETE for Channel 6
BIST PASS/FAIL for Channel 6
BIST COMPLETE for Channel 5
BIST PASS/FAIL for Channel 5
BIST COMPLETE for Channel 4
BIST PASS/FAIL for Channel 4
BIST COMPLETE for Channel 3
BIST PASS/FAIL for Channel 3
BIST COMPLETE for Channel 2
BIST PASS/FAIL for Channel 2
BIST COMPLETE for Channel 1
BIST PASS/FAIL for Channel 1
A "pass" indicates that the BER (Bit-Error-Rate) is better
than 10
-7
. This is a minimum test, so a "fail" indication means
that the BER is higher than 10
-7
.
The BIST features of the SCAN926260 six channel deseri-
alizer are compatible with the BIST features on the
DS92LV8028, the SCAN921023 and the SCAN921025 Se-
rializers.
BIST Alone Mode Selection
An important detail is that once both devices have the RUN-
BIST instruction loaded into their respective instruction reg-
isters, both devices must move into the RTI state within 4K
system clocks (At a system CLK of 66MHz and TCK of 1MHz
this allows for 66 TCK cycles). This is not a concern when
both devices are on the same scan chain or LSP. However,
it can be a problem with some multi-drop devices. This test
mode has been simulated and verified using National’s En-
hanced SCAN Bridge (SCANSTA111).
BIST Alone Test Modes
The SCAN926260 also supports a BISTAlone feature which
can be run without enabling the JTAG TAP controller. This
feature provides the ability to run continuous BER testing on
all channels, or on individual channels without affecting live
traffic on other channels. The ability to run the BERT (Bit-
Error-Rate-Test) while adjacent channels are carrying nor-
mal traffic is a useful tool to determine how normal traffic will
affect the BER on any given channel.
The BIST Alone features can be accessed using the 5 pins
defined as BIST_SEL0, BIST_SEL1, BIST_SEL2, BIS-
T_ACT, and BISTMODE_REQ.
BIST_ACT activates the BIST Alone mode. The BIST Alone
mode will continue until deactivated by the BIST_ACT pin.
The BIST_ACT input must be high or low for four or more
clock cycles in order to activate or deactivate the BISTAlone
mode. The BIST_ACT input is pulled low internally.
BISTMODE_REQ is used to select either gross error report-
ing or a specific output error report. When the BIST Alone
mode is active, the LOCKn output for all channels running
BIST Alone will go low and the respective ROUTn(0:9) out-
put will report any errors. When BISTMODE_REQ is low, the
error reporting is set to Gross Mode, and whenever a bit
contains one or more errors, ROUT(0:9) for that channel
goes high and stays high until deactivation by the BIST_ACT
input. When BISTMODE_REQ is high, the output error re-
porting is set to Bit Error mode. Whenever any data bit
contains an error, the data output for that corresponding bit
goes high. The default setting is Gross Error mode.
The three BIST_SELn inputs determine which channel is in
BIST Alone mode according to the following table:
BIST_ACT
1
1
1
1
1
1
1
1
0
BIST_SEL2
0
0
0
0
1
1
1
1
X
BIST_SEL1
0
0
1
1
0
0
1
1
X
BIST_SEL0
0
1
0
1
0
1
0
1
X
BIST for Channel
0
1
2
3
4
5
All Channels
IDLE
IDLE
S
www.national.com
11
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SCAN926260TUF | Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
| SCAN926260TUFX | Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
| SCAN928028 | 8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST |
| SCAN928028TUF | 8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST |
| SCAN928028TUFX | 8 Channel 10:1 Serializer with IEEE 1149.1 and At-Speed BIST |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCAN926260_03 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
| SCAN926260_08 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
| SCAN926260TUF | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN926260TUF/NOPB | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
| SCAN926260TUFX | 功能描述:LVDS 接口集成電路 RoHS:否 制造商:Texas Instruments 激勵器數(shù)量:4 接收機(jī)數(shù)量:4 數(shù)據(jù)速率:155.5 Mbps 工作電源電壓:5 V 最大功率耗散:1025 mW 最大工作溫度:+ 85 C 封裝 / 箱體:SOIC-16 Narrow 封裝:Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。