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參數(shù)資料
| 型號(hào)： | SCAN921821 |
| 廠(chǎng)商： | National Semiconductor Corporation |
| 英文描述： | Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1(JTAG), and At-Speed BIST |
| 中文描述： | 雙18位串行器與預(yù)加重，設(shè)有IEEE 1149.1（JTAG），并在速度BIST |
| 文件頁(yè)數(shù)： | 10/11頁(yè) |
| 文件大小： | 629K |
| 代理商： | SCAN921821 |
Pin Descriptions
Pin Name
DATA PINS
DINA0-17
DINB0-17
DOUTAP
DOUTAN
DOUTBP
DOUTAN
TIMING AND CONTROL PINS
Pin Count
I/O, Type
Description
18
18
1
1
1
1
I, LVCMOS
Transmitter inputs. There is a pull-down circuitry on each of these pins which are
active if respective PWDNA or PWDNB pin is pulled high.
O,BLVDS
Inverting and non-inverting differential transmitter outputs.
TxCLK
1
I, LVCMOS
Transmitter reference clock. Used to strobe data at the inputs and to drive the
transmitter PLL. There is a pull-up circuitry on this pin which is always active.
Transmitter outputs enable pins. There is a pull-down circuitry on each of these
pins that are active if corresponding PWDNA or PWDNB pin is pulled high.
When these pins are set to LOW, the transmitter outputs will be disabled. The
PLL will remain locked.
Stand-by mode pins. There is a pull-down circuitry on each of these pins that are
always active. When these pins are set to LOW, the transmitter will be put in low
power mode and the PLL will lose lock.
Transmitter synchronization pins. There is a pull-down circuitry on each of these
pins that are active if corresponding PWDNA or PWDNB pin is pulled high.
When these pins are set to HIGH, the transmitter will ignore incoming data and
send SYNC patterns to provide a locking reference to receiver(s).
ENA
1
I, LVCMOS
ENB
1
PWDNA
1
I, LVCMOS
PWDNB
1
SYNCA
1
I, LVCMOS
SYNCB
1
PRE-EMPHASIS PINS
PEMA0-2
3
I, LVCMOS
8-level pre-emphasis selection pins. There is a pull-down circuitry on each of
these pins which are active if corresponding PWDNA or PWDNB pin is pulled
high.
PEMB0-2
3
JTAG PINS
TDI
1
I, LVCMOS
Test Data Input to support IEEE 1149.1. There is a pull-up circuitry on this pin
which is always active.
Test Data Output to support IEEE 1149.1.
Test Mode Select Input to support IEEE 1149.1. There is a pull-up circuitry on
this pin which is always active.
Test Clock Input to support IEEE 1149.1. There is no failsafe circuitry on this pin.
Test Reset Input to support IEEE 1149.1. There is a pull-up circuitry on this pin
which is always active.
TDO
TMS
1
1
O, LVCMOS
I, LVCMOS
TCK
TRST
1
1
I, LVCMOS
I, LVCMOS
BIST PINS
BISTA
1
I, LVCMOS
BIST selection pins. These pins select which transmitter will generate a PRBS
like data. There is a pull-down circuitry on these pins which are active if
corresponding PWDNA or PWDNB pin is pulled high.
BISTB
1
POWER PINS
AVDD
DVDD
PVDD
AVSS
DVSS
PVSS
OTHER PINS
NC
6
8
5
5
10
5
I, POWER
I, POWER
I, POWER
I, POWER
I, POWER
I, POWER
Power Supply for the LVDS circuitry.
Power Supply for the digital circuitry.
Power Supply for the PLL and BG circuitry.
Ground reference for the LVDS circuitry.
Ground reference for the digital circuitry.
Ground reference for the PLL and BG circuitry.
1
N/A
Not connected.
S
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PDF描述 |
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| SCAN926260 | Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCAN921821TSM | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| SCAN921821TSM/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類(lèi)型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類(lèi)型:ECL/LVDS 輸出類(lèi)型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| SCAN926260 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
| SCAN926260_03 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
| SCAN926260_08 | 制造商:NSC 制造商全稱(chēng):National Semiconductor 功能描述:Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
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