- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄376339 > SCAN921260 (National Semiconductor Corporation) X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST PDF資料下載
參數(shù)資料
| 型號： | SCAN921260 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| 中文描述： | X6 1:10解串器與IEEE 1149.1（JTAG）及在速度BIST |
| 文件頁數(shù)： | 10/16頁 |
| 文件大?。?/td> | 379K |
| 代理商： | SCAN921260 |
Application Information
BIST Alone Mode Selection
(Continued)
BIST_ACT
1
1
1
1
1
1
1
1
0
BIST_SEL2
0
0
0
0
1
1
1
1
X
BIST_SEL1
0
0
1
1
0
0
1
1
X
BIST_SEL0
0
1
0
1
0
1
0
1
X
BIST for Channel
0
1
2
3
4
5
All Channels
IDLE
IDLE
POWER CONSIDERATIONS
An all CMOS design of the Deserializer makes it an inher-
ently low power device.
POWERING UP THE DESERIALIZER
The SCAN921260 can be powered up at any time by follow-
ing the proper sequence. The REFCLK input can be running
before the Deserializer powers up, and it must be running in
order for the Deserializer to lock to incoming data. The
Deserializer outputs will remain in TRI-STATE until the De-
serializer detects data transmission at its inputs and locks to
the incoming data stream.
TRANSMITTING DATA
Once you power up the Deserializer, it must be phase locked
to the transmitter to transmit data. Phase locking occurs
when the Deserializer locks to incoming data or when the
Serializer sends sync patterns. The Serializer sends SYNC
patterns whenever the SYNC1 or SYNC2 inputs are high.
The LOCKn output of the Deserializer remains high until it
has locked to the incoming data stream. Connecting the
LOCKn output of the Deserializer to one of the SYNC inputs
of the Serializer will guarantee that enough SYNC patterns
are sent to achieve Deserializer lock.
The Deserializer can also lock to incoming data by simply
powering up the device and allowing the “random lock”
circuitry to find and lock to the data stream.
While the Deserializer LOCKn output is low, data at the
Deserializer outputs (ROUT0-9) are valid, except for the
specific case of loss of lock during transmission which is
further discussed in the "Recovering from LOCK Loss" sec-
tion below.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still
reliably receive data. Various environmental and systematic
factors include:
Serializer: TCLK jitter, V
CC
noise (noise bandwidth and
out-of-band noise)
Media: ISI, Large V
CM
shifts
Deserializer: V
CC
noise
RECOVERING FROM LOCK LOSS
In the case where the Deserializer loses lock during data
transmission, up to 1 cycle of data that was previously
received can be invalid. This is due to the delay in the lock
detection circuit. The lock detect circuit requires that invalid
clock information be received 2 times in a row to indicate
loss of lock. Since clock information has been lost, it is
possible that data was also lost during these cycles. There-
fore, after the Deserializer relocks to the incoming data
stream and the Deserializer LOCKn pin goes low, at least
one previous data cycle should be suspect for bit errors.
The Deserializer can relock to the incoming data stream by
making the Serializer resend SYNC patterns, as described
above, or by random locking, which can take more time,
depending on the data patterns being received.
HOT INSERTION
All the BusLVDS devices are hot pluggable if you follow a
few rules. When inserting, ensure the Ground pin(s) makes
contact first, then the VCC pin(s), and then the I/O pins.
When removing, the I/O pins should be unplugged first, then
the VCC, then the Ground. Random lock hot insertion is
illustrated in
Figure 10
.
PCB LAYOUT AND POWER SYSTEM
CONSIDERATIONS
Circuit board layout and stack-up for the SCAN921260
should be designed to provide noise-free power to the de-
vice. Good layout practice will separate high frequency or
high level inputs and outputs to minimize unwanted stray
noise pickup, feedback and interference. There are a few
common practices which should be followed when designing
PCB’s for Bus LVDS Signaling. Recommended layout prac-
tices are:
Use at least 4 PCB board layers (Bus LVDS signals,
ground, power, and TTL signals).
Power system performance may be greatly improved by
using thin dielectrics (4 to 10 mils) for power/ground
sandwiches. This increases the intrinsic capacitance of
the PCB power system which improves power supply
filtering, especially at high frequencies, and makes the
value and placement of external bypass capacitors less
critical.
Keep Serializers and Deserializers as close to the (Bus
LVDS port side) connector as possible.
Longer stubs lower the impedance of the bus, increase
the load on the Serializer, and lower the threshold margin
at the Deserializers. Deserializer devices should be
placed much less than one inch from slot connectors.
Because transition times are very fast on the Serializer
Bus LVDS outputs, reducing stub lengths as much as
possible is the best method to ensure signal integrity.
S
www.national.com
10
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SCAN921260UJB | X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| SCAN921260UJBX | X6 1:10 Deserializer with IEEE 1149.1 (JTAG) and at-speed BIST |
| SCAN921821 | Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1(JTAG), and At-Speed BIST |
| SCAN926260 | Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
| SCAN926260TUF | Six 1 to 10 Bus LVDS Deserializers with IEEE 1149.1 and At-Speed BIST |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SCAN921260UJB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| SCAN921260UJB/NOPB | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
| SCAN921260UJBX | 功能描述:IC DESERIALIZER X6 1:10 196-LBGA RoHS:否 類別:集成電路 (IC) >> 接口 - 串行器，解串行器 系列:SCAN 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- 功能:解串器 數(shù)據(jù)速率:2.5Gbps 輸入類型:串行 輸出類型:并聯(lián) 輸入數(shù):- 輸出數(shù):24 電源電壓:1.8 V ~ 3.3 V 工作溫度:-40°C ~ 105°C 安裝類型:表面貼裝 封裝/外殼:64-TQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-TQFP-EP（10x10） 包裝:管件 |
| SCAN921821 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Dual 18-Bit Serializer with Pre-emphasis, IEEE 1149.1(JTAG), and At-Speed BIST |
| SCAN921821TSM | 功能描述:串行器/解串器 - Serdes RoHS:否 制造商:Texas Instruments 類型:Deserializer 數(shù)據(jù)速率:1.485 Gbit/s 輸入類型:ECL/LVDS 輸出類型:LVCMOS 輸入端數(shù)量:1 輸出端數(shù)量:20 工作電源電壓:2.375 V to 2.625 V 工作溫度范圍:0 C to + 70 C 封裝 / 箱體:TQFP-64 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。