參數(shù)資料
型號(hào)： SCAN18373T
廠商： Fairchild Semiconductor Corporation
英文描述： Transparent Latch with 3-STATE Outputs
中文描述： 透明鎖存器與三態(tài)輸出
文件頁(yè)數(shù)： 9/12頁(yè)
文件大小： 99K
代理商： SCAN18373T
9
www.fairchildsemi.com
S
AC Operating Requirements
Normal Operation
Note 9:
Voltage Range 5.0 is 5.0V
±
0.5V.
AC Electrical Characteristics
Scan Test Operation
Note 10:
Voltage Range 5.0 is 5.0V
±
0.5V.
Note:
All propagation delays involving TCK are measured from the falling edge of TCK.
Symbol
Parameter
V
CC
T
A
=
+
25
°
C
C
L
=
50 pF
Guaranteed Minimum
T
A
=
40
°
C to
+
85
°
C
C
L
=
50 pF
Units
(V)
(Note 9)
t
S
Setup Time, H or L
5.0
3.0
3.0
ns
Data to LE
Hold Time, H or L
LE to Data
t
H
5.0
1.5
1.5
ns
t
W
LE Pulse Width
5.0
5.0
5.0
ns
Symbol
Parameter
V
CC
T
A
=
+
25
°
C
C
L
=
50 pF
Typ
T
A
=
40
°
C to
+
85
°
C
C
L
=
50 pF
Min
3.5
3.5
Units
(V)
(Note 10)
5.0
Min
3.5
3.5
Max
13.2
13.2
Max
14.5
14.5
t
PLH
,
t
PHL
t
PLZ
,
t
PHZ
t
PZL
,
t
PZH
t
PLH
,
t
PHL
Propagation Delay
TCK to TDO
ns
Disable Time
TCK to TDO
Enable Time
5.0
2.5
2.5
3.0
11.5
11.5
14.5
2.5
2.5
3.0
11.9
11.9
15.8
ns
5.0
ns
TCK to TDO
Propagation Delay
TCK to Data Out
3.0
5.0
5.0
14.5
18.0
18.0
3.0
5.0
5.0
15.8
19.8
19.8
5.0
ns
during Update-DR State
Propagation Delay
TCK to Data Out
t
PLH
,
t
PHL
5.0
5.0
5.0
18.6
18.6
5.0
5.0
20.2
20.2
ns
during Update-IR State
Propagation Delay
TCK to Data Out
t
PLH
,
t
PHL
5.0
5.5
19.9
5.5
21.5
ns
during Test Logic
Reset State
Propagation Delay
5.5
19.9
5.5
21.5
t
PLZ
,
t
PHZ
5.0
4.0
16.4
4.0
18.2
TCK to Data Out
during Update-DR State
Propagation Delay
4.0
16.4
4.0
18.2
ns
t
PLZ
,
t
PHZ
5.0
19.5
5.0
20.8
TCK to Data Out
during Update-IR State
Propagation Delay
5.0
5.0
19.5
5.0
20.8
ns
t
PLZ
,
t
PHZ
5.0
19.9
5.0
21.5
TCK to Data Out
during Test Logic
Reset State
5.0
ns
5.0
19.9
5.0
21.5
t
PZL
,
t
PZH
Propagation Delay
TCK to Data Out
during Update-DR State
5.0
5.0
18.9
18.9
5.0
5.0
20.9
20.9
5.0
ns
t
PZL
,
t
PZH
Propagation Delay
TCK to Data Out
during Update-IR State
6.5
6.5
22.4
22.4
6.5
6.5
24.2
24.2
5.0
ns
t
PZL
,
t
PZH
Propagation Delay
TCK to Data Out
during Test Logic
7.0
23.8
7.0
25.7
5.0
ns
7.0
23.8
7.0
25.7
Reset State
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