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參數(shù)資料
| 型號： | SC8164 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | 2.488 Gbit/sec to 2.7Gbit/sec 1:16 SONET/SDH Demux |
| 中文描述： | 2.488 Gb /秒的2.7Gbit/sec 1:16的SONET / SDH解復(fù)用 |
| 文件頁數(shù)： | 11/16頁 |
| 文件大?。?/td> | 153K |
| 代理商： | SC8164 |
VITESSE
SEMICONDUCTOR CORPORATION
Preliminary Datasheet
VSC8164
2.488 Gbit/sec to 2.7Gbit/sec
1:16 SONET/SDH Demux
Page 4
VITESSE SEMICONDUCTOR CORPORATION
G52239-0, Rev. 3.3
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
5/17/00
Decoupling of the power supplies is a critical element in maintaining the proper operation of the part. It is
recommended that the VCC power supply be decoupled using a 0.1F and 0.01F capacitor placed in parallel
on each VCC power supply pin as close to the package as possible. If room permits, a 0.001F capacitor should
also be placed in parallel with the 0.1
F and 0.01F capacitors mentioned above. Recommended capacitors are
low inductance ceramic SMT X7R devices. For the 0.1
F capacitor, a 0603 package should be used. The
0.01
F and 0.001F capacitors can be either 0603 or 0402 packages.
For low frequency decoupling, 47
F tantalum low inductance SMT caps should be sprinkled over the
board’s main +3.3V power supply and placed close to the C-L-C pi filter.
If the device is being used in an ECL environment with a -3.3V supply, then all references to decoupling
VCC must be changed to VEE, and all references to decoupling 3.3V must be changed to -3.3V.
AC Characteristics
Figure 5: AC Timing Waveforms
Figure 6: High Speed Input Timing
VALID DATA (1)
VALID DATA (2)
Parallel data clock output
Parallel data outputs
Parallel data clock output
CLK16O+
D(0...15)+
CLK32O+
tpdd
tpd32
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10D11 D12
High speed differential clock input
High speed differential serial data input
HSCLKI+
DI+
tdsu
tdh
D13D14 D15
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