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參數(shù)資料
| 型號： | SC68C94C1A |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | nullQuad universal asynchronous receiver/transmitter QUART |
| 中文描述： | 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC52 |
| 封裝： | PLASTIC, SOT-238-3, LCC-52 |
| 文件頁數(shù)： | 13/33頁 |
| 文件大?。?/td> | 215K |
| 代理商： | SC68C94C1A |
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Philips Semiconductors
Product specification
SC68C94
Quad universal asynchronous receiver/transmitter (QUART)
1995 May 1
13
Table 4.
Register Bit Formats, Duart ab. [duplicated for Duart cd]
(continued)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ISR (Interrupt Status Register)
I/O Port
Change
0 = No
1 = Yes
Delta
BREAKb
0 = No
1 = Yes
RxRDY/
FFULLb
0 = No
1 = Yes
TxRDYb
Counter
Ready
0 = No
1 = Yes
Delta
BREAKa
0 = No
1 = Yes
RxRDY/
FFULLa
0 = No
1 = Yes
TxRDYa
0 = No
1 = Yes
0 = No
1 = Yes
IMR (Interrupt Mask Register)
I/O Port
Change
INT
Delta
BREAKb
INT
RxRDY/
FFULLb
INT
TxRDYb
INT
Counter
Ready
INT
Delta
BREAKa
INT
RxRDY/
FFULLa
INT
TxRDYa
INT
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
0 = off
1 = on
CTUR (Counter/Timer Upper Register)
C/T[15]
C/T[14]
C/T[13]
C/T[12]
C/T[11]
C/T[10]
C/T[9]
C/T[8]
CTUR (Counter/Timer Lower Register)
C/T[7]
C/T[6]
C/T[5]
C/T[4]
C/T[3]
C/T[2]
C/T[1]
C/T[0]
IPR (Input Port Register)
I/O3b
I/O2b
I/O3a
I/O2a
I/O1b
I/O0b
I/O1a
I/O0a
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
0 = Low
1 = High
Mode Registers 0, 1 and 2
The addressing of the Mode Registers is controlled by the MR
Register pointer. On any access to the Mode Registers this pointer
is always incremented. Upon reaching a value of 2 it remains at 2
until changed by a CR command or a hardware reset.
MR0 – Mode Register 0
Mode Register 0 (MR0) is part of the UART configuration registers.
It controls the watch dog timer and the encoding of the number of
characters received in the RxFIFO. The lower four bits of this
register are not implemented in the hardware of the chip. MR0 is
normally set to either 80h or 00h. A read of this register will return
1111 (Fh) in the lower four bits.
The MR0 register is accessed by setting the MR Pointer to zero (0)
via the command register command 1011 (Bh).
MR0[7]:
This bit enables or disables the RxFIFO watch dog timer.
MR0[7] = 1 enable timer
MR0[7] = 0 disable timer
MR0[6:4]:
These bits are normally set to 0 except as noted in the
“Interrupt Threshold Calculation” description
MR0[3:0]:
These bits are not implemented in the chip. These bits
should be be considered “reserved.”
MR1 – Mode Register 1
MR1 is accessed when the MR pointer points to MR1. The pointer is
set to MR1 by RESET, a set pointer command applied via the CR or
after an access to MR0. After reading or writing MR1, the pointers
are set at MR2.
MR1[7] – Receiver Request-to-Send Flow Control
This bit controls the deactivation of the RTSN output (I/O2x) by the
receiver. This output is manually asserted and negated by
commands applied via the command register. MR1[7] = 1 causes
RTSN to be automatically negated upon receipt of a valid start bit if
the receiver FIFO is full. RTSN is re-asserted when an empty FIFO
position is available. This feature can be used to prevent overrun in
the receiver by using the RTSN output signal to control the CTS
input (the QUART I/O0 pin) of the transmitting device.
Use of this feature requires the I/O2 pin to be programmed as output
via the I/OPCR and to be driving a 0 via the OPR. When the RxFIFO
is full and the start bit of the ninth character is sensed the receiver
logic will drive the I/O2 pin high. This pin will return low when
another RxFIFO position is vacant.
MR1[6] – Receiver Interrupt Select 1
This bit is normally set to 0 except as noted in the “Interrupt
Threshold Calculation” description. MR1[6] operates with MR0[6] to
prevent the receiver from bidding until a particular fill level is
attained. For software compatibility this bit is designed to emulate
the RxFIFO interrupt function of previous Philips Semiconductors
UARTs.
MR1[5] – Error Mode Select
This bit selects the operating mode of the three FIFOed status bits
(received break, FE, PE). In the character mode, status is provided
on a character-by-character basis; the status applies only to the
character at the top of the FIFO.
In the block mode, the status provided in the SR for these bits is the
accumulation (logical-OR) of the status for all characters coming to
the top of the FIFO since the last reset error command was issued.
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