參數(shù)資料
型號(hào)： SC68C94A1N
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 50 psi, Gage, Cell with body o-ring, 10 Vdc excitation
中文描述： 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PDIP48
封裝： PLASTIC, DIP-48
文件頁數(shù)： 5/33頁
文件大小： 215K
代理商： SC68C94A1N
Philips Semiconductors
Product specification
SC68C94
Quad universal asynchronous receiver/transmitter (QUART)
1995 May 1
5
Table 1.
QUART Registers
1
A5:0
000000
000001
000010
000011
000100
000101
000110
000111
001000
001001
001010
001011
001100
001101
001110
001111
010000
010001
010010
010011
010100
010101
010110
010111
011000
011001
011010
011011
011100
011101
011110
011111
100000
100001
100010
100011
100100
100101
100110
100111
101000
101001
101010
101011
101100
101101
101110
101111
READ (RDN = Low)
WRITE (WRN = Low)
Mode Register a (MR0a, MR1a, MR2a)
Status Register a (SRa)
Reserved
Receive Holding Register a (RxFIFOa)
Input Port Change Reg ab (IPCRab)
Interrupt Status Reg ab (ISRab)
Counter/Timer Upper ab (CTUab)
Counter/Timer Lower ab (CTLab)
Mode Register b (MR0b, MR1b, MR2b)
Status Register b (SRb)
Reserved
Receive Holding Register b (RxFIFOb)
Output Port Register ab (OPRab)
Input Port Register ab (IPRab)
Start Counter ab
Stop Counter ab
Mode Register c (MR0c, MR1c, MR2c)
Status Register c (SRc)
Reserved
Receive Holding Register c (RxFIFOc)
Input Port Change Reg cd (IPCRcd)
Interrupt Status Reg cd (ISRcd)
Counter/Timer Upper cd (CTUcd)
Counter/Timer Lower cd (CTLcd)
Mode Register d (MR0d, MR1d, MR2d)
Status Register d (SRd)
Reserved
Receive Holding Register d (RxFIFOd)
Output Port Register cd (OPRcd)
Input Port Register cd (IPRcd)
Start Counter cd
Stop Counter cd
Bidding Control Register a (BCRa)
Bidding Control Register b (BCRb)
Bidding Control Register c (BCRc)
Bidding Control Register d (BCRd)
Reserved
Reserved
Reserved
Reserved
Current Interrupt Register (CIR)
Global Interrupting Channel Reg (GICR)
Global Int Byte Count Reg (GIBCR)
Global Receive Holding Reg (GRxFIFO)
Interrupt Control Register (ICR)
Reserved
Reserved
Reserved
Reserved
Test Mode
Reserved
Mode Register a (MR0a, MR1a, MR2a)
Clock Select Register a (CSRa)
Command Register a (CRa)
Transmit Holding Register a (TxFIFOa)
Auxiliary Control Reg ab (ACRab)
Interrupt Mask Reg ab (IMRab)
Counter/Timer Upper Reg ab (CTURab)
Counter/Timer Lower Reg ab (CTLRab)
Mode Register b (MR0b, MR1b, MR2b)
Clock Select Register b (CSRb)
Command Register b (CRb)
Transmit Holding Register b (TxFIFOb)
Output Port Register ab (OPRab)
I/OPCRa (I/O Port Control Reg a)
I/OPCRb (I/O Port Control Reg b)
Reserved
Mode Register c (MR0c, MR1c, MR2c)
Clock Select Register c (CSRc)
Command Register c (CRc)
Transmit Holding Register c (TxFIFOc)
Auxiliary Control Reg cd (ACRcd)
Interrupt Mask Reg cd (IMRcd)
Counter/Timer Upper Reg cd (CTURcd)
Counter/Timer Lower Reg cd (CTLRcd)
Mode Register d (MR0d, MR1d, MR2d)
Clock Select Register d (CSRd)
Command Register d (CRd)
Transmit Holding Register d (TxFIFOd)
Output Port Register cd (OPRcd)
I/OPCRc (I/O Port Control Reg c)
I/OPCRd (I/O Port Control Reg d)
Reserved
Bidding Control Register a (BCRa)
Bidding Control Register b (BCRb)
Bidding Control Register c (BCRc)
Bidding Control Register d (BCRd)
Power Down
Power Up
Disable DACKN
Enable DACKN
Reserved
Interrupt Vector Register (IVR)
Update CIR
Global Transmit Holding Reg (GTxFIFO)
Interrupt Control Register (ICR)
BRG Rate. 00 = low; 01 = high
Set X1/CLK divide by two
2
Set X1/CLK Normal
2
Reserved
Test Mode
Reserved
110000–111000
111001
111010–111111
NOTES:
1. Registers not explicitly reset by hardware reset power up randomly.
2. In X1/CLK divide by 2 all circuits receive the divided clock except the BRG and change-of-state detectors.
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