參數(shù)資料
型號(hào)： SC68C94A1A
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： nullQuad universal asynchronous receiver/transmitter QUART
中文描述： 4 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQCC52
封裝： PLASTIC, SOT-238-3, LCC-52
文件頁數(shù)： 10/33頁
文件大小： 215K
代理商： SC68C94A1A
Philips Semiconductors
Product specification
SC68C94
Quad universal asynchronous receiver/transmitter (QUART)
1995 May 1
10
period follows the period of the X1 clock. The maximum speed is
4.0MHz. If a higher speed X1 clock is used then the X1 clock “divide
by 2” feature must be used.
The value of the winning bid determined during the arbitration cycle
is compared to the “Interrupt Threshold” contained in the ICR
(Interrupt Control Register). If the winning bid exceeds the value of
the ICR the IRQN is asserted.
Priority Arbitration and Bidding
Each of the five “types” of interrupts has slightly different “bid” value,
as follows:
Receivers
# rcv’d
rEr
3
1
Transmitters
0
1
Break Detect
Programmable
Change of State
Programmable
Counter/Timer
Programmable
2
1
1
1
1
Chan #
2
# avail
3
1
1
0
1
Chan #
2
1
1
0
1
0
1
Chan #
2
3
0
1
0
1
1
1
Chan #
2
3
1
1
0
1
1
1
Chan #
2
0
1
SD00162
Bits shown above as ‘0’ or ‘1’ are hard-wired inputs to the arbitration
logic. Their presence allows determination of the interrupt type and
they insure that no bid will have a value of all zeros (a condition that
is indistinguishable from not bidding at all). They also serve to set a
default priority among the non-receive/transmit types when the
programmable fields are all zeros.
The channel number always occupies the two LSBs. Inclusion of
the channel number insures that a bid value generated will be
unique and that a single “winner” will drive the Interrupt Bus at the
end of the arbitration interval. The channel number portion of each
UARTs bid is hard-wired with UARTa being channel number 0 and
so forth.
As can be seen above, bits 4:2 of the winning bid value can be used
to identify the type of interrupt, including whether data was received
correctly or not. Like the Channel number field, these bits are
hard-wired for each interrupt source.
The “# rcv’d” and “# avail” fields indicate the number of bytes
present in the receiver FIFO and the number of empty bytes in the
transmitter FIFO, respectively.
NOTE: When there are zero bytes in the receiver’s FIFO, it does
NOT bid. Similarly, a full transmitter FIFO makes NO bid. In the
case where all bids have been disabled by the Interrupt Mask
Register or as a result of their byte counts, the active-low Interrupt
Bus will return FFh. This value always indicates no interrupt source
is active and IRQN will be negated.
The high order bit of the transmitter “bid” is always zero. An empty
transmit FIFO is, therefore, fixed at a lower interrupt priority than a
1/2 full receive FIFO. Bit 4 of a receiver bid is the Receiver Error Bit
(RER). The RER is the OR of the parity, framing and overrun error
conditions. The RER does little to modify the priority of receiver
interrupts vs. transmitter interrupts. It is output to the Interrupt Bus
to allow inclusion of good data vs. problem data information in the
Current Interrupt Register.
The high order bits of bids for received break, CoS (Change of
State) and Counter/Timer events are all programmable. By
programming ones in these fields, the associated interrupt source
can be made more significant than most receiver and all transmitter
interrupts. Values near zero in these fields makes them lower
priority classes of interrupt.
The channel address for C/T ab will be encoded as channel B (01)
The channel address for C/T cd will be encoded as channel D (11)
As shown in Figure 4, the bid arbitration process is controlled by the
EVAL/HOLDN signal derived from the oscillator clock.
Receipt of an IACKN signal from the host MPU latches the latest
“winning bid” from the latched Interrupt Bus into the Current Interrupt
Register (CIR). This logic is diagrammed in Figure 5.
If the IACKN falling edge of Figure 4 occurs during EVAL time, the
result from the last arbitration (captured by the Interrupt Bus latches)
is stored in CIR. Otherwise, the next EVAL pulse is inhibited and the
value in the Interrupt Bus Latches is stored in CIR.
Clearing the Interrupt
Activities which change the state of the ISR will cause the IRQN to
assert or negate. In addition, the accessing of a global or local
RxFIFO or TxFIFO reduces the associated byte count for transmitter
and receiver data interrupts. If the byte count falls below the
threshold value, the interrupt request is withdrawn. Other interrupt
conditions are cleared when the interrupting source is cleared.
Once the interrupt is cleared, the programmable value lowered or its
byte count value reduced by one of the methods listed above, a
different bidder (or no bidder at all) will win the on-going arbitration.
When the winning bid drops below the Interrupt Threshold
Register’s value, the IRQN pin will negate.
Arbitration - Aftermath
At the end of the arbitration, i.e., the falling edge of EVAL, the
winning interrupt source is driving its Channel number, number of
bytes (if applicable) and interrupt type onto the Interrupt Bus. These
values are captured into a latch by the trailing edge of EVAL. The
output of this latch is used by the Interrupt Threshold comparator;
the winning value is captured into another set of latches called the
Current Interrupt Register (CIR) at the time of an Interrupt
Acknowledge cycle or execution of the “Update CIR” command.
The Current Interrupt Register and associated read logic is shown in
Figure 5. Interrupting channel number and the three bit interrupt
type code and FIFO fill level are readable via the Internal Data Bus.
The contents of the appropriate receiver or transmitter byte
“counter”, as captured at the time of IACKN assertion, make up bits
7:5 of the CIR. If the interrupt type stored in the Current Interrupt
Register is not a receiver or transmitter data transfer type, the
CIR7:5 field will read as the programmable fields of their respective
bid formats.
The buffers driving the CIR to the DBUS also provide the means of
implementing the Global Interrupting Channel and Global Byte
Count Registers, described in a later section.
The winning bid channel number and interrupt type fields can also
be used to generate part of the Interrupt Vector, as defined by the
Interrupt Control Register.
Interrupt Context
The channel number of the winning “bid” is used by the address
decoders to provide data from the interrupting UART channel via a
set of Global pseudo-registers. The interrupt Global
pseudo-registers are:
1. Global Interrupting Byte Count
2. Global Interrupting Channel
3. Global Receive Holding Register
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