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參數(shù)資料
| 型號(hào)： | SC4250LISTRT |
| 廠商： | Semtech |
| 文件頁(yè)數(shù)： | 7/12頁(yè) |
| 文件大?。?/td> | 231K |
| 描述： | IC HOT SWAP CTRLR 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無(wú) |
| 電源電壓： | 10 V ~ 80 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SO |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 其它名稱： | SC4250LISDKR |
7
POWER MANAGEMENT
SC4250
Applications Information (Cont.)
user must determine the level of the current where it should
trip. As a rule of thumb, the over-current is set to be 200-
300% of the nominal value. In our case, we assumed this
value to be 5A.
Considering the minimum trip voltage is 50mV the value
of R4 is 50mV ?5A = 10 m&.
The tolerance of this resistor is usually price driven and 5%
is an adequate range of accuracy.
The actual position and layout of the circuitry around the
sense resistor R4 is critical to avoid a false over-current
tripping. The trace routing between R4 and SC4250 should
be as short as possible and wide enough to handle the
maximum current with zero current in the sense lines
ideally Kelvin like. Additionally, there is a short delay
circuit at the comparator to filter out unwanted noise and
otherwise induced transients.
Inrush Current is being controlled by the R5C3 network
and swamping capacitor C2.
When a board is plugged into a live backplane, the input
bulk capacitance of the boards power supply produces
large current transients due to the rush of the currents
charging those capacitors. The main feature of the SC4250
is to provide an orderly and well-controlled inrush current.
Since the minimum trip voltage is 50mV, lets choose the
inrush current to be 3A.
Imax = Cload ?Vmax /dt
dt = Cload ? Vmax /Imax = 150礔 ?70V / 3A = 3.5ms
This would be the minimum time for the gate voltage
plateau during which the Vdd linearly decreases
maintaining 3A charge current of the Cload.
The inrush can be calculated using the following equation:
I
MAX
= (50?/SPAN>A " C
LOAD
) / C3
With the values shown in the schematic the actual inrush
current will be about 2A, which is within the limits we have
chosen.
Resistor R5 will produce a time constant which prevents
Q1 from turning on when power is initially applied and the
circuit is not ready to actively pull the gate low. Its value
is not critical and 18k ensures the adequate delay.
The value of C2 is chosen to prevent false turn-on of the
FET due to the current flowing via C3 into the gate of the
FET when the circuit initially connects to the power source.
Capacitors C2 and C3 form a divider from Vin to GND. C2
must keep the initial voltage at the gate below Vth
minimum.
For the typical FET, this threshold is around 1V to 2V,
therefore C2 = 100 " C3 will keep gate voltage at 0.7V,
even at the worst case of Vin = 70V.
The choice of the Q1 is quite straightforward and is guided
mostly by thermal considerations due to the power
dissipation in the steady state.
For instance, in our case, the nominal current is 2A, the
power dissipation due to the conducting losses will be
Pdis = Inom?" Rds_on.
The MOSFET should be able to withstand Vdss e 100V
with continuous drain current Id e 6A. Device SUD06N10
or similar fits this application. It has an Rds_on = 0.2&,
and will dissipate
Pdis = 2?" 0.2 = 0.8W, which can be handled by this
DPAK device.
If there is a consideration of reducing the temperature of
the MOSFET then the lower Rds_on device should be chosen
or a different style (D2PAK) which has lower Junction-to-
Ambient thermal characteristics.
The R6
has a function of dumping high frequency
oscillations. The value of it is not critical and can be in the
range of 5& to 20&.
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