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參數(shù)資料
| 型號： | SC26C92C1N,602 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART DUAL W/FIFO 40-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Stand-Alone UARTs |
| 標(biāo)準(zhǔn)包裝： | 9 |
| 特點： | 收發(fā)器 |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 8 字節(jié) |
| 電源電壓： | 5V |
| 帶自動流量控制功能： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 40-DIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 40-DIP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 828 (CN2011-ZH PDF) |
| 其它名稱： | 568-1208-5 935051520602 SC26C92C1N |
2010 Fairchild Semiconductor Corporation
www.fairchildsemi.com
FLXA2203 Rev. 1.0.5
12
FXLA2203
—
Dual-Mode,
Dual-SI
M-Card
Level
Translator
Power-Up / Power-Down Sequence
Table 4. Power Supply Pins
Pin
Name
Function
1
VCC
EN and CH_Swap Supply
2
VCC_H_1
Host 1 Supply
3
VCC_H_2
Host 2 Supply
4
VCC1
Power Switch 1 Input
5
VCC2
Power Switch 2 Input
The VCC host power sequencing is non preferential;
however, VCC must be higher or equal to VCC1 and VCC2.
The Enable pin must be LOW while VCC1 and VCC2 ramp
up to valid supply voltages or ramp down to 0V.
A pull-up resistor tying enable to ground should be used
to ensure that bus contention, excessive currents, or
oscillations do not occur during power up or power
down. The size of the pull-up resistor is based upon the
current sinking capability of the device driving the
Enable pin.
Recommended power-up sequence (see Figure 16):
1.
Apply power to VCC.
2.
Assert EN LOW (FXLA2203 disabled).
3.
Apply power to VCC1, VCC2, VCC_H_1, and
VCC_H_2.
4.
Assert EN HIGH (FXLA2203 enabled).
5.
Begin activation timing (see Figure 14).
Recommended power-down sequence (see Figure 17):
1. Complete deactivation timing (see Figure 15).
2. Assert EN LOW (FXLA2203 disabled).
3. Ramp down power to VCC1, VCC2, VCC_H_1,
and VCC_H_2.
4. Once VCC1 and VCC2 are OFF, ramp down VCC.
VCC_Cardn
RST_n
CLK_n
I/O_n
EN
CH_Swap
VCC1, VCC2
VCC_H_n
RST_H_n
CLK_H_n
I/O_H_n
ZZZ
Z
ZZZ
Z
ZZZ
Z
ZZZ
Z
VCC
AB C
Power-Up
Sequencing
Begin Activation
Timing per ISO7816
3 2006
Card
Po
rts
Host
P
or
ts
Figure 16. Power-Up Sequencing
Figure 17. Power-Down Sequencing
Notes:
23. A=VCC becomes a valid voltage, EN=LOW.
24. B=VCC1, VCC2, and VCC_H_n become valid
voltages, EN=LOW.
25. C=FXLA2203 enabled (EN goes HIGH), ready for
activation (ISO7816-3).
Notes:
26. A=Disable FXLA2203, bring EN LOW.
27. B=Ramp down VCC1, VCC2, and VCC_H_n.
28. C=Ramp down VCC once VCC1 and VCC2 are off.
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