參數(shù)資料
型號(hào)： SC26C562C1N
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： CMOS dual universal serial communications controller CDUSCC
中文描述： 2 CHANNEL(S), 10M bps, MULTI PROTOCOL CONTROLLER, PDIP48
封裝： PLASTIC, DIP-48
文件頁(yè)數(shù)： 6/22頁(yè)
文件大?。?/td> 151K
代理商： SC26C562C1N
Philips Semiconductors
Product specification
SC26C562
CMOS dual universal serial communications controller
(CDUSCC)
1998 Sep 04
6
PIN DESCRIPTION
MNEMONIC
PIN NO.
TYPE
NAME AND FUNCTION
DIP
4-2,
47-45
31-28,
21-18
PLCC
4-2,
51-49
33-30,
23-20
A1–A6
I
Address Lines:
Active-high. Address inputs which specify which of the internal registers
is accessed for read/write operation.
Bidirectional Data Bus:
Active-high, 3-State. Bit 0 is the LSB and bit 7 is the MSB. All
data, command and status transfers between the CPU and the CDUSCC take place over
this bus. The data bus is enabled when CSN and RDN, or CSN and WRRN are low during
interrupt acknowledge cycles and single address DMA acknowledge cycles.
D0–D7
I/O
RDN
22
24
I
Read Strobe:
Active-low input. When active and CSN is also active, causes the content
of the addressed register to be present on the data bus. RDN is ignored unless CSN is
active.
WRN
26
28
I
Write Strobe:
Active-low input. When active and CSN is also active, the content of the
data bus is loaded into the addressed register. The transfer occurs on the rising edge of
WRN. WRN is ignored unless CEN is active.
CSN
25
27
I
Chip Select:
Active-low input. When active, data transfers between the CPU and the
CDUSCC are enabled on D0–D7 as controlled by RDN or WRN and A1–A6 inputs. When
CSN is high, the data lines are placed in the 3-State condition (except during interrupt
acknowledge cycles and single address DMA transfers).
RDYN
7
8
O
Ready:
Active-low, open drain. Used to synchronize data transfers between the CPU and
the CDUSCC. It is valid only during read and write cycles where the CDUSCC is
configured in ‘wait on Rx’, ‘wait on Tx’ or ‘wait on Tx or Rx’ modes, otherwise it is always
inactive. RDYN becomes active on the leading edge of RDN and WRN if the requested
operation cannot be performed (viz, no data in RxFIFO in the case of a read or no room in
the TxFIFO in the case of a write).
IRQN
6
6
O
Interrupt Request:
Active-low, open-drain. This output is asserted upon occurrence of
any enabled interrupting condition. The CPU can read the general status register to
determine the interrupting condition(s), or can respond with an interrupt acknowledge cycle
to cause the CDUSCC to output an interrupt vector on the data bus.
IACKN
1
1
I
Interrupt Acknowledge:
Active-low. When IACKN is asserted, the CDUSCC responds
by either forcing the bus into high-impedance, placing a vector number, call instruction or
zero on the data bus. The vector number can be modified or unmodified by the status. If
no interrupt is pending, IACKN is ignored and the data bus placed in high-impedance.
X1/CLK
43
47
I
Crystal or External Clock:
When using the crystal oscillator, the crystal is connected
between pins X1 and X2. If a crystal is not used, an external clock is supplied at this input.
This clock is used to drive the internal bit rate generator, as an optional input to the
counter/timer or DPLL, and to provide other required clocking signals. When a crystal is
used, a capacitor must be connected from this pin to ground.
X2
42
46
O
Crystal 2:
Connection for other side of crystal. When a crystal is used, a capacitor must
be connected from this pin to ground. If an external clock is used on X1, this pin should be
left floating.
RESETN
23
25
I
Master Reset:
Active-low. A low on this pin resets the transmitters and receivers and
resets the registers shown in Table 1 of the CDUSCC Users’ Guide. Reset is
asynchronous, i.e., no clock is required.
RxDA, RxDB
37, 12
40, 14
I
Channel A (B) Receiver Serial Data Input:
The least significant bit is received first. If
external receiver clock is specified for the channel, the input is sampled on the rising edge
of the clock.
TxDA, TxDB
36, 13
39, 15
O
Channel A (B) Transmitter Serial Data Output:
The least significant bit is transmitted
first. This output is in the marking (high) condition when the transmitter is disabled or when
the channel is operating in local loopback mode. If external transmitter clock is specified
for the channel, the data is shifted on the falling edge of the clock.
RTxCA, RTxCB
39, 10
43, 11
I/O
Channel A (B) Receiver/Transmitter Clock:
As an input, it can be programmed to
supply the receiver, transmitter, counter/timer, or DPLL clock. As an output, it can supply
the counter/timer output, the transmitter shift clock (1X), or the receiver sampling clock
(1X).
TRxCA, TRxCB
40, 9
44, 10
I/O
Channel A (B) Transmitter/Receiver Clock:
As an input, it can supply the receiver,
transmitter, counter/timer, or DPLL clock. As an output, it can supply the counter/timer
output, the DPLL output, the transmitter shift clock (1X), the receiver sampling clock (1X),
the transmitter BRG clock (16X), The receiver BRG clock (16X), or the internal system
clock (X1
÷
2).
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SC26C92 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual universal asynchronous receiver/transmitter DUART
SC26C92A1A 功能描述:UART 接口集成電路 UART DUAL W/FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC26C92A1A,512 功能描述:UART 接口集成電路 UART DUAL W/FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC26C92A1A,518 功能描述:UART 接口集成電路 5V 2 CH UART IND TEMP RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC26C92A1A,529 功能描述:UART 接口集成電路 5V 2CH UART IND TEMP RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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