參數資料
型號: SC16IS752IPW-T
廠商: NXP Semiconductors
文件頁數: 36/60頁
文件大?。?/td> 0K
描述: IC UART DUAL I2C/SPI 28-TSSOP
標準包裝: 2,500
特點: 低電流
通道數: 2,DUART
FIFO's: 64 字節(jié)
規(guī)程: RS232,RS485
電源電壓: 2.5V, 3.3V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 28-TSSOP(0.173",4.40mm 寬)
供應商設備封裝: 28-TSSOP
包裝: 帶卷 (TR)
配用: 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
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C
16IS
752
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s
doc
umen
tis
s
ubj
ect
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l
egal
di
sc
lai
mer
s
.
NX
P
B
.V
.20
12.
A
llr
ight
s
r
es
er
v
ed
.
Prod
uct
dat
a
sh
eet
Rev
.
9
22
March
2012
41
of
6
0
NXP
Semiconductors
SC16IS752;
SC16IS762
D
u
al
UART
with
I 2
C-b
u
s/SPI
int
e
rf
ace
,
6
4
-b
yt
e
FIFOs
,IrDA
SIR
1
.SPI
operation
R/W = 0; A[3:0] = register address; CH[1:0] = 00 for channel A; CH[1:0] = 01 for channel B
a. Register write
R/W = 1; A[3:0] = register address; CH[1:0] = 00 for channel A; CH[1:0] = 01 for channel B
b. Register read
R/W = 0; A[3:0] = 0000; CH[1:0] = 00 for channel A; CH[1:0] = 01 for channel B
c. FIFO write cycle
R/W = 1; A[3:0] = 0000; CH[1:0] = 00 for channel A; CH[1:0] = 01 for channel B
d. FIFO read cycle
(1) Last bit (D0) of the last byte to be written to the transmit FIFO.
(2) Last bit (D0) of the last byte to be read from the receive FIFO.
Fig 20. SPI operation
SI
A1
A2
A3
R/W
SCLK
CH1
A0
X
CH0
D6
D7
D4
D5
D2
D3
D0
D1
002aab433
SI
A1
A2
A3
R/W
SCLK
CH1
A0
X
CH0
002aab434
SO
D6
D7
D4
D5
D2
D3
D0
D1
SI
A1
A2
A3
R/W
SCLK
CH1
A0
X
CH0
D6
D7
D4
D5
D2
D3
D0
D1
002aab435
D6
D7
D4
D5
D2
D3
D0
D1
last bit(1)
SI
A1
A2
A3
R/W
SCLK
CH1
A0
X
CH0
002aab436
SO
D6
D7
D4
D5
D2
D3
D0
D1
D0
D1
last bit(2)
D6
D7
D4
D5
D2
D3
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