參數(shù)資料
型號: SC16C850IET,115
廠商: NXP Semiconductors
文件頁數(shù): 40/55頁
文件大小: 0K
描述: IC UART SINGLE W/FIFO 36-TFBGA
標準包裝: 1,000
特點: 可編程
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.5 V ~ 3.3 V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 36-TFBGA
供應(yīng)商設(shè)備封裝: 36-TFBGA(3.5x3.5)
包裝: 帶卷 (TR)
其它名稱: 935284685115
SC16C850IET-G
SC16C850IET-G-ND
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
45 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
(1) INT is active when TX FIFO is empty or TX FIFO drops below trigger level.
(2) INT is cleared when ISR is read or TX FIFO fills up to trigger level.
Fig 19. Transmit timing in 16 mode
active
transmitter ready
active
16 baud rate clock
002aac413
td(IOW-INTL)
INT(1)(2)
IOW
active
D0
D1
D2
D3
D4
D5
D6
D7
TX
5 data bits
6 data bits
7 data bits
stop
bit
parity
bit
start
bit
data bits (0 to 7)
next data
start
bit
td(start-INT)
td(IOW-TX)
(1) IRQ is active when TX FIFO is empty or TX FIFO drops below trigger level.
(2) IRQ is cleared when ISR is read or TX FIFO fills up to trigger level.
Fig 20. Transmit timing in 68 mode
D0
D1
D2
D3
D4
D5
D6
D7
active
TX ready
active
16 baud rate clock
002aac634
td(CS-IRQH)W
start
bit
td(start-IRQL)
TX
IRQ(1)(2)
CS (write)
data bits (0 to 7)
active
td(CS-TX)W
5 data bits
6 data bits
7 data bits
parity
bit
stop
bit
next data
start
bit
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