參數(shù)資料
型號(hào): SC16C850IBS,151
廠商: NXP Semiconductors
文件頁(yè)數(shù): 6/55頁(yè)
文件大小: 0K
描述: IC UART SGL-CH 3.3V 32-HVQFN
標(biāo)準(zhǔn)包裝: 490
特點(diǎn): 可編程
通道數(shù): 1,UART
FIFO's: 128 字節(jié)
規(guī)程: RS485
電源電壓: 2.5 V ~ 3.3 V
帶自動(dòng)流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 828 (CN2011-ZH PDF)
其它名稱: 568-4778
935283103151
SC16C850
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 2 — 11 November 2010
14 of 55
NXP Semiconductors
SC16C850
2.5 to 3.3 V UART with 128-byte FIFOs and IrDA encoder/decoder
each time the Receive Holding Register (RHR) is read. The actual time-out value is
4 character time, including data information length, start bit, parity bit, and the size of stop
bit, that is, 1
×, 1.5×, or 2× bit times.
6.9 Programmable baud rate generator
The SC16C850 UART contains a programmable rational baud rate generator that takes
any clock input and divides it by a divisor in the range between 1 and (216
1). The
SC16C850 offers the capability of dividing the input frequency by rational divisor. The
fractional part of the divisor is controlled by the CLKPRES register in the ‘first extra feature
register set’.
(1)
where:
N is the integer part of the divisor in DLL and DLM registers;
M is the fractional part of the divisor in CLKPRES register;
fXTAL1 is the clock frequency at XTAL1 pin.
Prescaler = 1 when MCR[7] is set to 0.
Prescaler = 4 when MCR[7] is set to 1.
A single baud rate generator is provided for the transmitter and receiver. The
programmable Baud Rate Generator is capable of operating with a frequency of up to
80 MHz. To obtain maximum data rate, it is necessary to use full rail swing on the clock
input. The SC16C850 can be configured for internal or external clock operation. For
internal clock operation, an industry standard crystal is connected externally between the
XTAL1 and XTAL2 pins (see Figure 7). Alternatively, an external clock can be connected
to the XTAL1 pin (see Figure 8) to clock the internal baud rate generator for standard or
custom rates (see Table 7).
The generator divides the input 16
× clock by any divisor from 1 to (216 1). The
SC16C850 divides the basic external clock by 16. The baud rate is configured via the
CLKPRES, DLL and DLM internal register functions. Customized baud rates can be
achieved by selecting the proper divisor values for the MSB and LSB sections of the baud
rate generator.
Fig 6.
Prescalers and baud rate generator block diagram
baud rate
f
XTAL1
MCR 7
[]
16
N
M
16
------
+
×
-------------------------------------------------------------------
=
002aac645
OSCILLATOR
XTAL1
XTAL2
DIVIDE-BY-1
DIVIDE-BY-4
CLKPRES
[3:0]
BAUD RATE
GENERATOR
(DLL, DLM)
transmitter and
receiver clock
MCR[7] = 0
MCR[7] = 1
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