參數(shù)資料
型號: SC16C754BIB80,557
廠商: NXP Semiconductors
文件頁數(shù): 17/50頁
文件大小: 0K
描述: IC UART QUAD W/FIFO 80-LQFP
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標(biāo)準(zhǔn)包裝: 595
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應(yīng)商設(shè)備封裝: 80-LQFP(12x12)
包裝: 管件
產(chǎn)品目錄頁面: 828 (CN2011-ZH PDF)
其它名稱: 568-1207
935274939557
SC16C754BIB80
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
24 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.3 FIFO Control Register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table 11
shows FIFO control register bit settings.
Table 11.
FIFO control register bits description
Bit
Symbol
Description
7:6
FCR[7] (MSB),
FCR[6] (LSB)
RX trigger. Sets the trigger level for the RX FIFO.
00 — 8 characters
01 — 16 characters
10 — 56 characters
11 — 60 characters
5:4
FCR[5] (MSB),
FCR[4] (LSB)
TX trigger. Sets the trigger level for the TX FIFO.
00 — 8 spaces
01 — 16 spaces
10 — 32 spaces
11 — 56 spaces
FCR[5:4] can only be modied and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.
3
FCR[3]
DMA mode select.
logic 0 = set DMA mode 0
logic 1 = set DMA mode 1
2
FCR[2]
Reset TX FIFO.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
1
FCR[1]
Reset RX FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This
bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO
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