參數(shù)資料
型號(hào): SC16C754BIA68,512
廠商: NXP Semiconductors
文件頁(yè)數(shù): 6/50頁(yè)
文件大?。?/td> 0K
描述: IC UART QUAD 64BYTE 68PLCC
標(biāo)準(zhǔn)包裝: 18
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC
包裝: 管件
其它名稱: 935274938512
SC16C754BIA68
SC16C754BIA68-ND
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
14 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
UART1 begins transmission and sends 52 characters, at which point UART2 will generate
an interrupt to its processor to service the RX FIFO, but assumes the interrupt latency is
fairly long. UART1 will continue sending characters until a total of 60 characters have
been sent. At this time, UART2 will transmit a 0Fh to UART1, informing UART1 to halt
transmission. UART1 will likely send the 61st character while UART2 is sending the Xoff
character. Now UART2 is serviced and the processor reads enough data out of the RX
FIFO that the level drops to 32. UART2 will now send a 0Dh to UART1, informing UART1
to resume transmission.
6.4 Reset
Table 4 summarizes the state of register after reset.
Remark: Registers DLL, DLM, SPR, Xon1, Xon2, Xoff1, Xoff2 are not reset by the
top-level reset signal RESET, that is, they hold their initialization values during reset.
Table 5 summarizes the state of registers after reset.
Table 4.
Register reset functions
Register
Reset control
Reset state
Interrupt enable register
RESET
all bits cleared
Interrupt identication register
RESET
bit 0 is set; all other bits cleared
FIFO control register
RESET
all bits cleared
Line control register
RESET
reset to 0001 1101 (1Dh)
Modem control register
RESET
all bits cleared
Line status register
RESET
bit 5 and bit 6 set; all other bits cleared
Modem status register
RESET
bits 3:0 cleared; bits 7:4 input signals
Enhanced feature register
RESET
all bits cleared
Receiver holding register
RESET
pointer logic cleared
Transmitter holding register
RESET
pointer logic cleared
Transmission control register
RESET
all bits cleared
Trigger level register
RESET
all bits cleared
Table 5.
Signal RESET functions
Signal
Reset control
Reset state
TX
RESET
HIGH
RTS
RESET
HIGH
DTR
RESET
HIGH
RXRDY
RESET
HIGH
TXRDY
RESET
LOW
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