參數(shù)資料
型號： SC16C754B
廠商： NXP Semiconductors N.V.
英文描述： 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
中文描述： 5伏，3.3伏和2.5伏兆5四異步/秒（最大）64字節(jié)的FIFO
文件頁數(shù)： 22/50頁
文件大?。?/td> 259K
代理商： SC16C754B
9397 750 14668
Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 13 June 2005
22 of 50
Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Table 10
lists and describes the SC16C754B internal registers.
[1]
These registers are accessible only when LCR[7] = 0.
[2]
This bit can only be modified if register bit EFR[4] is enabled, that is, if enhanced functions are enabled.
[3]
The Special Register set is accessible only when LCR[7] is set to a logic 1.
[4]
Enhanced Feature Register; Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to ‘BFh’.
Table 10:
SC16C754B internal registers
A2 A1 A0 Register Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read/
Write
General Register set
[1]
0
0
0
0
0
0
0
0
1
RHR
THR
IER
bit 7
bit 7
0/CTS
interrupt
enable
[2]
RX
trigger
level
(MSB)
FCR[0]
bit 6
bit 6
0/RTS
interrupt
enable
[2]
RX trigger
level (LSB)
bit 5
bit 5
0/Xoff
[2]
bit 4
bit 4
0/X Sleep
mode
[2]
bit 3
bit 3
modem
status
interrupt
DMA
mode
select
bit 2
bit 2
receive
line status
interrupt
TX FIFO
reset
bit 1
bit 1
THR
empty
interrupt
RX FIFO
reset
bit 0
bit 0
Rx data
available
interrupt
FIFO
enable
R
W
R/W
0
1
0
FCR
0/TX
trigger
level
(MSB)
[2]
0/CTS,
RTS
0/TX
trigger
level
(LSB)
[2]
0/Xoff
W
0
1
0
IIR
FCR[0]
interrupt
priority
bit 2
parity
enable
interrupt
priority
bit 1
number of
stop bits
interrupt
priority
bit 0
word
length
bit 1
RTS
interrupt
status
R
0
1
1
LCR
DLAB
break
control bit
set parity
paritytype
select
word
length
bit 0
DTR
R/W
1
0
0
MCR
1
×
or
1
×
/4
clock
[2]
0/error in
RX FIFO
CD
bit 7
bit 7
bit 7
RX FIFO
D status
TCR and
TLR
enable
[2]
THR and
TSR empty
RI
bit 6
bit 6
bit 6
RX FIFO
C status
0/Xon
Any
[2]
0/enable
loop-back
IRQ
enable
OP
framing
error
CD
bit 3
bit 3
bit 3
TXFIFO
D status
FIFO
ready
enable
parity error overrun
R/W
1
0
1
LSR
THR
empty
DSR
bit 5
bit 5
bit 5
RX FIFO
B status
break
interrupt
CTS
bit 4
bit 4
bit 4
RX FIFO
A status
error
DSR
bit 1
bit 1
bit 1
TX FIFO
B status
data in
receiver
CTS
bit 0
bit 0
bit 0
TX FIFO
A status
R
1
1
1
1
1
1
1
1
1
1
0
1
0
1
1
MSR
SPR
TCR
TLR
FIFO
Rdy
RI
bit 2
bit 2
bit 2
TX FIFO
C status
R
R/W
R/W
R/W
R
Special Register set
[3]
0
0
0
0
0
1
Enhanced Register set
[4]
0
1
0
EFR
DLL
DLH
bit 7
bit 15
bit 6
bit 14
bit 5
bit 13
bit 4
bit 12
bit 3
bit 11
bit 2
bit 10
bit 1
bit 9
bit 0
bit 8
R/W
R/W
Auto CTS Auto RTS
Special
character
detect
Enable
enhanced
functions
[2]
software
flow
control
bit 3
bit 3
bit 3
bit 3
bit 3
software
flow
control
bit 2
bit 2
bit 2
bit 2
bit 2
software
flow
control
bit 1
bit 1
bit 1
bit 1
bit 1
software
flow
control
bit 0
bit 0
bit 0
bit 0
bit 0
R/W
1
1
1
1
0
0
1
1
0
1
0
1
Xon1
Xon2
Xoff1
Xoff2
bit 7
bit 7
bit 7
bit 7
bit 6
bit 6
bit 6
bit 6
bit 5
bit 5
bit 5
bit 5
bit 4
bit 4
bit 4
bit 4
R/W
R/W
R/W
R/W
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