參數(shù)資料
型號: SC16C752IB48,128
廠商: NXP Semiconductors
文件頁數(shù): 45/47頁
文件大小: 0K
描述: IC DUAL UART 64BYTE 48LQFP
標準包裝: 1
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 標準包裝
其它名稱: 568-5955-6
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
7 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
The SC16C752 has selectable hardware ow control and software ow control.
Hardware ow control signicantly reduces software overhead and increases system
efciency by automatically controlling serial data ow using the RTS output and CTS
input signals. Software ow control automatically controls data ow by using
programmable Xon/Xoff characters.
The UART includes a programmable baud rate generator that can divide the timing
reference clock input by a divisor between 1 and (216
1).
6.1 Trigger levels
The SC16C752 provides independent selectable and programmable trigger levels for
both receiver and transmitter DMA and interrupt generation. After reset, both
transmitter and receiver FIFOs are disabled and so, in effect, the trigger level is the
default value of one byte. The selectable trigger levels are available via the FCR. The
programmable trigger levels are available via the TLR.
6.2 Hardware ow control
Hardware ow control is comprised of Auto-CTS and Auto-RTS. Auto-CTS and
Auto-RTS can be enabled/disabled independently by programming EFR[7:6].
With Auto-CTS, CTS must be active before the UART can transmit data.
Auto-RTS only activates the RTS output when there is enough room in the FIFO to
receive data and de-activates the RTS output when the RX FIFO is sufciently full.
The halt and resume trigger levels in the TCR determine the levels at which RTS is
activated/deactivated.
If both Auto-CTS and Auto-RTS are enabled, when RTS is connected to CTS, data
transmission does not occur unless the receiver FIFO has empty space. Thus,
overrun errors are eliminated during hardware ow control. If not enabled, overrun
errors occur if the transmit data rate exceeds the receive FIFO servicing latency.
Fig 3.
Autoow control (Auto-RTS and Auto-CTS) example.
RX
FIFO
SERIAL-TO-
PARALLEL
FLOW
CONTROL
TX
FIFO
PARALLEL-
TO-SERIAL
FLOW
CONTROL
PARALLEL-
TO-SERIAL
FLOW
CONTROL
SERIAL-TO-
PARALLEL
FLOW
TX
FIFO
RX
FIFO
UART 1
UART 2
D7-D0
RX
TX
RTS
CTS
TX
RX
CTS
RTS
D7-D0
CONTROL
002aaa228
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