參數(shù)資料
型號: SC16C752BIBS,157
廠商: NXP Semiconductors
文件頁數(shù): 15/47頁
文件大?。?/td> 0K
描述: IC DUAL UART 64BYTE 32HVQFN
標(biāo)準(zhǔn)包裝: 2,450
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 托盤
其它名稱: 935276389157
SC16C752BIBS
SC16C752BIBS-ND
SC16C752B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 — 30 November 2010
22 of 47
NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.3 FIFO Control Register (FCR)
This is a write-only register that is used for enabling the FIFOs, clearing the FIFOs, setting
transmitter and receiver trigger levels, and selecting the type of DMA signalling. Table 11
shows FIFO control register bit settings.
Table 11.
FIFO Control Register bits description
Bit
Symbol
Description
7:6
FCR[7] (MSB),
FCR[6] (LSB)
RX trigger. Sets the trigger level for the receive FIFO.
00 - 8 characters
01 - 16 characters
10 - 56 characters
11 - 60 characters
5:4
FCR[5] (MSB),
FCR[4] (LSB)
TX trigger. Sets the trigger level for the transmit FIFO.
00 - 8 spaces
01 - 16 spaces
10 - 32 spaces
11 - 56 spaces
FCR[5:4] can only be modified and enabled when EFR[4] is set. This is
because the transmit trigger level is regarded as an enhanced function.
3
FCR[3]
DMA mode select.
logic 0 = set DMA mode ‘0’
logic 1 = set DMA mode ‘1’
2
FCR[2]
Reset transmit FIFO.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = Clears the contents of the transmit FIFO and resets the FIFO
counter logic (the transmit shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
1
FCR[1]
Reset receive FIFO.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = Clears the contents of the receive FIFO and resets the FIFO
counter logic (the receive shift register is not cleared or altered). This bit
will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFO enable.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO.
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