參數(shù)資料
型號: SC16C752BIBS,151
廠商: NXP Semiconductors
文件頁數(shù): 19/47頁
文件大?。?/td> 0K
描述: IC UART DUAL W/FIFO 32-HVQFN
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標(biāo)準(zhǔn)包裝: 490
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-HVQFN(5x5)
包裝: 托盤
產(chǎn)品目錄頁面: 828 (CN2011-ZH PDF)
其它名稱: 568-3288
935276389151
SC16C752BIBS-S
SC16C752B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 — 30 November 2010
26 of 47
NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
7.7 Modem Status Register (MSR)
This 8-bit register provides information about the current state of the control lines from the
mode, data set, or peripheral device to the processor. It also indicates when a control
input from the modem changes state. Table 15 shows Modem Status Register bit settings
per channel.
[1]
The primary inputs RIn, CDn, CTSn, DSRn are all active LOW, but their registered equivalents in the MSR
and MCR (in Loopback) registers are active HIGH.
Table 15.
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
CD (active HIGH, logic 1)[1]. This bit is the complement of the CDn input
during normal mode. During internal Loopback mode, it is equivalent to
MCR[3].
6
MSR[6]
RI (active HIGH, logic 1)[1]. This bit is the complement of the RIn input during
normal mode. During internal Loopback mode, it is equivalent to MCR[2].
5
MSR[5]
DSR (active HIGH, logic 1)[1]. This bit is the complement of the DSRn input
during normal mode. During Internal Loopback mode, it is equivalent MCR[0].
4
MSR[4]
CTS (active HIGH, logic 1)[1]. This bit is the complement of the CTSn input
during normal mode. During internal Loopback mode, it is equivalent to
MCR[1].
3MSR[3]
ΔCD. Indicates that CDn input (or MCR[3] in Loopback mode) has changed
state. Cleared on a read.
2MSR[2]
ΔRI. Indicates that RIn input (or MCR[2] in Loopback mode) has changed
state from LOW to HIGH. Cleared on a read.
1MSR[1]
ΔDSR. Indicates that DSRn input (or MCR[0] in Loopback mode) has changed
state. Cleared on a read.
0MSR[0]
ΔCTS. Indicates that CTSn input (or MCR[1] in Loopback mode) has changed
state. Cleared on a read.
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