參數(shù)資料
型號： SC16C750BIBS,128
廠商： NXP Semiconductors
文件頁數(shù)： 9/44頁
文件大?。?/td> 0K
描述： IC UART 64BYTE 32HVQFN
標準包裝： 6,000
通道數(shù)： 1，UART
FIFO's： 64 字節(jié)
電源電壓： 2.5V，3.3V，5V
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶調制解調器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 32-VFQFN 裸露焊盤
供應商設備封裝： 32-HVQFN（5x5）
包裝： 帶卷 (TR)
其它名稱： 935276388128
SC16C750BIBS-F
SC16C750BIBS-F-ND
SC16C750B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 October 2008
17 of 44
NXP Semiconductors
SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
7.2.1 IER versus Receive FIFO interrupt mode operation
When the receive FIFO (FCR[0] = logic 1), and receive interrupts (IER[0] = logic 1) are
enabled, the receive interrupts and register status will reect the following:
The receive data available interrupts are issued to the external CPU when the FIFO
has reached the programmed trigger level. It will be cleared when the FIFO drops
below the programmed trigger level.
FIFO status will also be reected in the user accessible ISR register when the FIFO
trigger level is reached. Both the ISR register status bit and the interrupt will be
cleared when the FIFO drops below the trigger level.
The data ready bit (LSR[0]) is set as soon as a character is transferred from the shift
register to the receive FIFO. It is reset when the FIFO is empty.
7.2.2 IER versus Receive/Transmit FIFO polled mode operation
When FCR[0] = logic 1, resetting IER[3:0] enables the SC16C750B in the FIFO polled
mode of operation. Since the receiver and transmitter have separate bits in the LSR,
either or both can be used in the polled mode by selecting respective transmit or receive
control bit(s).
LSR[0] will be a logic 1 as long as there is one byte in the receive FIFO.
LSR[4:1] will provide the type of errors encountered, if any.
LSR[5] will indicate when the transmit FIFO is empty.
LSR[6] will indicate when both the transmit FIFO and transmit shift register are empty.
LSR[7] will indicate any FIFO data errors.
1
IER[1]
Transmit Holding Register interrupt. This interrupt will be issued whenever the
THR is empty, and is associated with LSR[1].
logic 0 = disable the transmitter empty interrupt (normal default condition)
logic 1 = enable the transmitter empty interrupt
0
IER[0]
Receive Holding Register interrupt. This interrupt will be issued when the FIFO
has reached the programmed trigger level, or is cleared when the FIFO drops
below the trigger level in the FIFO mode of operation.
logic 0 = disable the receiver ready interrupt (normal default condition)
logic 1 = enable the receiver ready interrupt
Table 9.
Interrupt Enable Register bits description …continued
Bit
Symbol
Description
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相關代理商/技術參數(shù)
參數(shù)描述
SC16C750BIBS-F 功能描述:UART 接口集成電路 16CB 2.5V-5V 1CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C750BIBS-S 制造商:NXP Semiconductors 功能描述:UART 1-CH 64Byte FIFO 2.5V/3.3V/5V 32-Pin HVQFN EP Tray
SC16C750IA44 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Universal Asynchronous Receiver/Transmitter (UART) with 64-byte FIFO
SC16C750IA44,512 功能描述:UART 接口集成電路 16C 2.5V-5V 1CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC16C750IA44,518 功能描述:UART 接口集成電路 16C 2.5V-5V 1CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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