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參數(shù)資料
| 型號： | SC16C650BIN40 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder/decoder |
| 中文描述： | 1 CHANNEL(S), 3M bps, SERIAL COMM CONTROLLER, PDIP40 |
| 封裝： | 0.600 INCH, PLASTIC, MO-015, SOT-129-1, DIP-40 |
| 文件頁數(shù)： | 13/51頁 |
| 文件大?。?/td> | 881K |
| 代理商： | SC16C650BIN40 |
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Philips Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
Product data
Rev. 03 — 10 December 2004
13 of 51
9397 750 14451
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
characters are not placed (stacked) in the user accessible RX data buffer or FIFO.
When using a software flow control the Xon/Xoff characters cannot be used for data
transfer.
In the event that the receive buffer is overfilling and flow control needs to be executed,
the SC16C650B automatically sends an Xoff message (when enabled) via the serial
TX output to the remote modem. The SC16C650B sends the Xoff1,2 characters as
soon as received data passes the programmed trigger level. To clear this condition,
the SC16C650B will transmit the programmed Xon1,2 characters as soon as receive
data drops below the next low or programmed trigger level.
6.5 Special feature software flow control
A special feature is provided to detect an 8-bit character when EFR[5] is set. When
8-bit character is detected, it will be placed on the user-accessible data stack along
with normal incoming RX data. This condition is selected in conjunction with
EFR[0:3]. Note that software flow control should be turned off when using this special
mode by setting EFR[0:3] to a logic 0.
The SC16C650B compares each incoming receive character with Xoff2 data. If a
match exists, the received data will be transferred to the FIFO, and ISR[4] will be set
to indicate detection of a special character. Although the Internal Register Table
(
Table 8
) shows each X-Register with eight bits of character information, the actual
number of bits is dependent on the programmed word length. Line Control Register
bits LCR[0:1] define the number of character bits, i.e., either 5 bits, 6 bits, 7 bits or
8 bits. The word length selected by LCR[0:1] also determine the number of bits that
will be used for the special character comparison. Bit 0 in the X-registers corresponds
with the LSB bit for the receive character.
6.6 Hardware/software and time-out interrupts
Three special interrupts have been added to monitor the hardware and software flow
control. The interrupts are enabled by IER[5:7]. Care must be taken when handling
these interrupts. Following a reset, the transmitter interrupt is enabled, the
SC16C650B will issue an interrupt to indicate that the Transmit Holding Register is
empty. This interrupt must be serviced prior to continuing operations. The ISR
register provides the current singular highest priority interrupt only. It could be noted
that CTS and RTS interrupts have lowest interrupt priority. A condition can exist
where a higher priority interrupt may mask the lower priority CTS/RTS interrupt(s).
Only after servicing the higher pending interrupt will the lower priority CTS/TRS
interrupt(s) be reflected in the status register. Servicing the interrupt without
investigating further interrupt conditions can result in data errors.
When two interrupt conditions have the same priority, it is important to service these
interrupts correctly. Receive Data Ready and Receive Time Out have the same
interrupt priority (when enabled by IER[0]). The receiver issues an interrupt after the
number of characters have reached the programmed trigger level. In this case, the
SC16C650B FIFO may hold more characters than the programmed trigger level.
Following the removal of a data byte, the user should re-check LSR[0] for additional
characters. A Receive Time Out will not occur if the receive FIFO is empty. The
time-out counter is reset at the center of each stop bit received or each time the
receive holding register (RHR) is read. The actual time-out value is 4 character time.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SC16C652B | 5V, 3.3 V and 2.5V dual UART, 5 Mbit/s (max.),with 32-byte FIFOs and infrared(IrDA) encoder/decoder |
| SC16C652 | Dual UART with 32 bytes of transmit and receive FIFOs |
| SC16C652IB48 | Dual UART with 32 bytes of transmit and receive FIFOs |
| SC16C654IB64 | Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder |
| SC16C654 | Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C650BIN40,112 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 1CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C652 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual UART with 32 bytes of transmit and receive FIFOs |
| SC16C652B | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:5V, 3.3 V and 2.5V dual UART, 5 Mbit/s (max.),with 32-byte FIFOs and infrared(IrDA) encoder/decoder |
| SC16C652BIB48 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH UART 32B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C652BIB48,128 | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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