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鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� SC16C554DBIB64,151
寤犲晢锛� NXP Semiconductors
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 26/57闋�(y猫)
鏂囦欢澶у皬锛� 0K
鎻忚堪锛� IC UART QUAD W/FIFO 64-LQFP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Stand-Alone UARTs
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 160
閫氶亾鏁�(sh霉)锛� 4锛孮UART
FIFO's锛� 16 瀛楃瘈(ji茅)
闆绘簮闆诲锛� 2.5V锛�3.3V锛�5V
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甯舵晠闅滃暉鍕�(d貌ng)浣嶆娓�(c猫)鍔熻兘锛� 鏄�
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瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 64-LQFP
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 64-LQFP锛�10x10锛�
鍖呰锛� 鎵樼洡
鐢�(ch菐n)鍝佺洰閷勯爜(y猫)闈細 827 (CN2011-ZH PDF)
鍏跺畠鍚嶇ū锛� 568-3270
935276669151
SC16C554DBIB64-S
2010-2012 Microchip Technology Inc.
DS41413C-page 33
PIC12(L)F1822/PIC16(L)F1823
Bank 2
100h(1)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
101h(1)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
102h(1)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
103h(1)
STATUS
鈥�
鈥擳O
PD
ZDC
C
---1 1000 ---q quuu
104h(1)
FSR0L
Indirect Data Memory Address 0 Low Pointer
0000 0000 uuuu uuuu
105h(1)
FSR0H
Indirect Data Memory Address 0 High Pointer
0000 0000 0000 0000
106h(1)
FSR1L
Indirect Data Memory Address 1 Low Pointer
0000 0000 uuuu uuuu
107h(1)
FSR1H
Indirect Data Memory Address 1 High Pointer
0000 0000 0000 0000
108h(1)
BSR
鈥�
BSR<4:0>
---0 0000 ---0 0000
109h(1)
WREG
Working Register
0000 0000 uuuu uuuu
10Ah(1)
PCLATH
鈥�
Write Buffer for the upper 7 bits of the Program Counter
-000 0000 -000 0000
10Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
0000 000x 0000 000u
10Ch
LATA
鈥�
鈥擫ATA5
LATA4
鈥擫ATA2
LATA1
LATA0
--xx -xxx --uu -uuu
10Dh
鈥�
Unimplemented
鈥�
10Eh
LATC(2)
鈥�
LATC5
LATC4
LATC3
LATC2
LATC1
LATC0
--xx xxxx --uu uuuu
10Fh
鈥�
Unimplemented
鈥�
110h
鈥�
Unimplemented
鈥�
111h
CM1CON0
C1ON
C1OUT
C1OE
C1POL
鈥�
C1SP
C1HYS
C1SYNC 0000 -100 0000 -100
112h
CM1CON1
C1INTP
C1INTN
C1PCH<1:0>
鈥�
C1NCH1(2) C1NCH0
0000 ---0 0000 ---0
113h
CM2CON0(2)
C2ON
C2OUT
C2OE
C2POL
鈥�
C2SP
C2HYS
C2SYNC 0000 -100 0000 -100
114h
CM2CON1(2)
C2INTP
C2INTN
C2PCH<1:0>
鈥�
C2NCH<1:0>
0000 --00 0000 --00
115h
CMOUT
鈥�
鈥擬C2OUT(2) MC1OUT ---- --00 ---- --00
116h
BORCON
SBOREN
鈥�
BORRDY 1--- ---q u--- ---u
117h
FVRCON
FVREN
FVRRDY
TSEN
TSRNG
CDAFVR<1:0>
ADFVR<1:0>
0q00 0000 0q00 0000
118h
DACCON0
DACEN
DACLPS
DACOE
鈥�
DACPSS<1:0>
鈥�
000- 00-- 000- 00--
119h
DACCON1
鈥�
DACR<4:0>
---0 0000 ---0 0000
11Ah
SRCON0
SRLEN
SRCLK<2:0>
SRQEN
SRNQEN
SRPS
SRPR
0000 0000 0000 0000
11Bh
SRCON1
SRSPE
SRSCKE
SRSC2E(2)
SRSC1E
SRRPE
SRRCKE
SRRC2E
(2)
SRRC1E 0000 0000 0000 0000
11Ch
鈥�
Unimplemented
鈥�
11Dh
APFCON
RXDTSEL
SDOSEL
SSSEL
---
T1GSEL
TXCKSEL
P1BSEL
CCP1SEL 000- 0000 000- 0000
11Eh
鈥�
Unimplemented
鈥�
11Fh
鈥�
Unimplemented
鈥�
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as 鈥�0鈥�.
Note
1:
These registers can be addressed from any bank.
2:
PIC16(L)F1823 only.
3:
Unimplemented. Read as 鈥�1鈥�.
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