參數(shù)資料
型號(hào): SC16C550BIA44,518
廠商: NXP Semiconductors
文件頁(yè)數(shù): 2/48頁(yè)
文件大?。?/td> 0K
描述: IC UART SINGLE W/FIFO 44-PLCC
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標(biāo)準(zhǔn)包裝: 1
特點(diǎn): 可編程
通道數(shù): 1,UART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線(xiàn))
供應(yīng)商設(shè)備封裝: 44-PLCC
包裝: 標(biāo)準(zhǔn)包裝
產(chǎn)品目錄頁(yè)面: 827 (CN2011-ZH PDF)
其它名稱(chēng): 568-2039-6
SC16C550B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 1 October 2008
10 of 48
NXP Semiconductors
SC16C550B
5 V, 3.3 V and 2.5 V UART with 16-byte FIFOs
6.1 Internal registers
The SC16C550B provides 12 internal registers for monitoring and control. These registers
are shown in Table 3. These registers function as data holding registers (THR/RHR),
interrupt status and control registers (IER/ISR), a FIFO Control Register (FCR), line status
and control registers (LCR/LSR), modem status and control registers (MCR/MSR),
programmable data rate (clock) control registers (DLL/DLM), and a user accessible
scratchpad register (SPR). Register functions are more fully described in the following
paragraphs.
[1]
These registers are accessible only when LCR[7] is a logic 0.
[2]
These registers are accessible only when LCR[7] is a logic 1.
6.2 FIFO operation
The 16-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
bit 0 (FCR[0]). With 16C550 devices, the user can set the receive trigger level, but not the
transmit trigger level. The receiver FIFO section includes a time-out function to ensure
data is delivered to the external CPU. An interrupt is generated whenever the Receive
Holding Register (RHR) has not been read following the loading of a character or the
receive trigger level has not been reached.
Table 3.
Internal registers decoding
A2
A1
A0
Read mode
Write mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR/LSR, SPR)[1]
0
Receive Holding Register
Transmit Holding Register
0
1
Interrupt Enable Register
0
1
0
Interrupt Status Register
FIFO Control Register
0
1
Line Control Register
1
0
Modem Control Register
1
0
1
Line Status Register
n/a
1
0
Modem Status Register
n/a
1
Scratchpad Register
Baud rate register set (DLL/DLM)[2]
0
LSB of Divisor Latch
0
1
MSB of Divisor Latch
Table 4.
Flow control mechanism
Selected trigger level
(characters)
INT pin activation
Negate RTS
Assert RTS
11
1
0
44
4
0
88
8
0
14
0
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