參數(shù)資料
型號(hào): SC16C2550BIB48,128
廠商: NXP Semiconductors
文件頁(yè)數(shù): 23/31頁(yè)
文件大小: 0K
描述: IC UART DUAL W/FIFO 48-LQFP
標(biāo)準(zhǔn)包裝: 2,000
特點(diǎn): 故障啟動(dòng)位檢測(cè)
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 帶卷 (TR)
其它名稱: 935274406128
SC16C2550BIB48-F
SC16C2550BIB48-F-ND
40
2570N–AVR–05/11
ATmega325/3250/645/6450
10.9.2
PRR – Power Reduction Register
Bits 7:4 - Reserved bits
These bits are reserved bits in Atmel ATmega325/3250/645/6450 and will always read as zero.
Bit 3 - PRTIM1: Power Reduction Timer/Counter1
Writing logic one to this bit shuts down the Timer/Counter1 module. When Timer/Counter1 is
enabled, operation will continue like before the shutdown.
Bit 2 - PRSPI: Power Reduction Serial Peripheral Interface
Writing logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock to
the module. When waking up the SPI again, the SPI should be re-initialized to ensure proper
operation.
Bit 1 - PRUSART: Power Reduction USART
Writing logic one to this bit shuts down the USART by stopping the clock to the module. When
waking up the USART again, the USART should be re-initialized to ensure proper operation.
Bit 0 - PRADC: Power Reduction ADC
Writing logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.
The analog comparator cannot use the ADC input MUX when the ADC is shut down.
The Analog Comparator is disabled using the ACD-bit in the “ACSR – Analog Comparator Control and Sta-
Bit
765
4
3
2
1
0
PRTIM1
PRSPI
PRUSART0
PRADC
PRR
Read/Write
R
R/W
Initial Value
0
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