參數(shù)資料
型號: SC16C2550B
廠商: NXP Semiconductors N.V.
英文描述: 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
中文描述: 5伏,3.3伏和2.5伏兆5雙UART /秒(最大),16字節(jié)的FIFO
文件頁數(shù): 14/42頁
文件大?。?/td> 200K
代理商: SC16C2550B
Philips Semiconductors
SC16C2550B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
Product data
Rev. 02 — 14 December 2004
14 of 42
9397 750 14449
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
data that is then made available at the user data interface D0-D7. The user optionally
compares the received data to the initial transmitted data for verifying error-free
operation of the UART TX/RX circuits.
In this mode, the receiver and transmitter interrupts are fully operational. The Modem
Control Interrupts are also operational.
Fig 6.
Internal loop-back mode diagram.
TRANSMIT
FIFO
REGISTER
TXA, TXB
RECEIVE
SHIFT
REGISTER
RECEIVE
FIFO
REGISTER
RXA, RXB
I
A
C
SC16C2550B
TRANSMIT
SHIFT
REGISTER
MODEM
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
XTAL2
XTAL1
DATA BUS
AND
CONTROL LOGIC
D0–D7
IOR
IOW
RESET
A0–A2
CSA, CSB
REGISTER
SELECT
LOGIC
INTA, INTB
TXRDYA, TXRDYB
RXRDYA, RXRDYB
INTERRUPT
CONTROL
LOGIC
002aaa599
MCR[4] = 1
CTSA, CTSB
RTSA, RTSB
DSRA, DSRB
DTRA, DTRB
RIA, RIB
(OP1A, OP1B)
CDA, CDB
(OP2A, OP2B)
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