
388
AMD Geode SC1200/SC1201 Processor Data Book
Electrical Specifications
32579B
9.3.6
PCI Bus
The SC1200/SC1201 processor is compliant with PCI bus
v2.1 specification. Relevant information from the PCI bus
specification is provided below.
All parameters in
Table 9-20 are not 100% tested. The
parameters in this table are further described in
Figure 9-Figure 9-13. Testing Setup for PCI Slew Rate and Minimum Timing
Table 9-20. PCI AC Specifications
Symbol
Parameter
Min
Max
Unit
Comments
IOH(AC)
(Note 1)
Switching current high
-12VIO
mA
0 < VOUT ≤ 0.3VIO,
-17.1(VIO-VOUT)mA
0.3VIO < VOUT < 0.9VIO
Equation A
0.7VIO < VOUT < VIO
Test point (Note 2)
-32VIO
mA
VOUT = 0.7VIO
IOL(AC)
Switching current low
16VIO
mA
VIO > VOUT ≥ 0.6VIO
26.7VOUT
mA
0.6VIO > VOUT > 0.1VIO
Equation B
0.18VIO>VOUT>0
38VIO
mA
VOUT = 0.18VIO
ICL
Low clamp current
-25+(VIN+1)/0.015
mA
-3 < VIN < -1
ICH
High clamp current
25+(VIN-VIO-1)/0.015
mA
VIO+4 > VIN > VIO+1
SLEWR
(Note 3)
Output rise slew rate
1
4
V/ns
0.2VIO - 0.6VIO Load
SLEWF
Output fall slew rate
1
4
V/ns
0.6VIO - 0.2VIO Load
Note 1. Refer to the V/I curves in
Figure 9-14. This specification does not apply to PCICLK0, PCICLK1, and PCIRST# which
are system outputs.
Note 2. Maximum current requirements are met when drivers pull beyond the first step voltage. Equations which define
these maximum values (A and B) are provided with relevant diagrams in
Figure 9-14. These maximum values are
guaranteed by design.
Note 3. Rise slew rate does not apply to open-drain outputs. This parameter is interpreted as the cumulative edge rate
across the specified range, according to the test circuit in
Figure 9-13.Buffer
VCC
0.5" max.
Pin
1 K
Ω
1 K
Ω
10 pF
Output