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參數(shù)資料
| 型號： | SC1101CS |
| 廠商： | Semtech Corporation |
| 英文描述： | VOLTAGE MODE PWM CONTROLLER |
| 中文描述： | 電壓模式PWM控制器 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大?。?/td> | 96K |
| 代理商： | SC1101CS |
SC1101
2000 SEMTECH CORP.
652 MITCHELL ROAD NEWBURY PARK CA 91320
VOLTAGE MODE PWM CONTROLLER
February 29, 2000
5
LAYOUT GUIDELINES
Careful attention to layout requirements are necessary
for successful implementation of the SC1101 PWM con-
troller. High currents switching at 200kHz are present in
the application and their effect on ground plane voltage
differentials must be understood and minimized.
1). The high power parts of the circuit should be laid out
first. A ground plane should be used, the number and
position of ground plane interruptions should be such as
to not unnecessarily compromise ground plane integrity.
Isolated or semi-isolated areas of the ground plane may
be deliberately introduced to constrain ground currents
to particular areas, for example the input capacitor and
bottom Schottky ground.
2). The loop formed by the Input Capacitor(s) (Cin), the
Top FET (Q1) and the Schottky (D1) must be kept as
small as possible. This loop contains all the high current,
fast transition switching. Connections should be as wide
and as short as possible to minimize loop inductance.
Minimizing this loop area will reduce EMI, lower ground
injection currents, resulting in electrically “cleaner”
grounds for the rest of the system and minimize source
ringing, resulting in more reliable gate switching signals.
3). The connection between the junction of Q1, D1 and
the output inductor should be a wide trace or copper re-
gion. It should be as short as practical. Since this con-
nection has fast voltage transitions, keeping this connec-
tion short will minimize EMI. The connection between the
output inductor and the sense resistor should be a wide
trace or copper area, there are no fast voltage or current
transitions in this connection and length is not so impor-
tant, however adding unnecessary impedance will re-
duce efficiency.
4) The Output Capacitor(s) (Cout) should be located as
close to the load as possible, fast transient load currents
are supplied by Cout only, and connections between
Cout and the load must be short, wide copper areas to
minimize inductance and resistance.
5) The SC1101 is best placed over an isolated ground
plane area. GND and PGND should be returned to this
isolated ground. This isolated ground area should be
connected to the main ground by a trace that runs from
the GND pin to the ground side of (one of) the output ca-
pacitor(s). If this is not possible, the GND pin may be
connected to the ground path between the Output Ca-
pacitor(s) and the Cin, Q1, D1 loop. Under no circum-
stances should GND be returned to a ground inside the
Cin, Q1, D1 loop.
6) Vcc for the SC1101 should be supplied from the 5V
supply through a 10
resistor, the Vcc pin should be de-
coupled directly to GND by a 0.1
μ
F ceramic capacitor,
trace lengths should be as short as possible.
Vout
5V
4uH
5mOhm
+
Cout
+
Cin
10
0.1uF
2.32k
1.00k
Q1
0.1uF
12V IN
Heavy lines indicate
high current paths.
D1
SC1101CS
GND
8
VCC
1
CS(-)
2
CS(+)
3
PGND
4
DH
5
BST
6
FB
7
Rb
Ra
Fig. 5 Layout diagram for the SC1101
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