XC878CLM
Functional Description
Data Sheet
87
V1.1, 2009-08
The following formulas calculate the final baud rate without and with the fractional divider
respectively:
(3.4)
(3.5)
The maximum baud rate that can be generated is limited to
f
PCLK/32. Hence, for a module
clock of 24 MHz, the maximum achievable baud rate is 0.75 MBaud.
Standard LIN protocol can support a maximum baud rate of 20 kHz, the baud rate
accuracy is not critical and the fractional divider can be disabled. Only the prescaler is
used for auto baud rate calculation. For LIN fast mode, which supports the baud rate of
20 kHz to 57.6 kHz, the higher baud rates require the use of the fractional divider for
greater accuracy.
Table 30 lists the various commonly used baud rates with their corresponding parameter
settings and deviation errors. The fractional divider is disabled and a module clock of
24 MHz is used.
The fractional divider allows baud rates of higher accuracy (lower deviation error) to be
generated. Table 31 lists the resulting deviation errors from generating a baud rate of
57.6 kHz, using different module clock frequencies. The fractional divider is enabled
(fractional divider mode) and the corresponding parameter settings are shown.
Table 30
Typical Baud rates for UART with Fractional Divider disabled
Baud rate
Prescaling Factor
(2BRPRE)
Reload Value
(BR_VALUE + 1)
Deviation Error
19.2 kBaud
1 (BRPRE=000B)
78 (4EH)0.17 %
9600 Baud
1 (BRPRE=000B)
156 (9CH)0.17 %
4800 Baud
2 (BRPRE=001B)
156 (9CH)0.17 %
2400 Baud
4 (BRPRE=010B)
156 (9CH)0.17 %
baud rate
fPCLK
16 2
BRPRE
BR_VALUE 1
+
()
×
-----------------------------------------------------------------------------------
where 2
BRPRE
BR_VALUE 1
+
() 1
>
×
=
baud rate
fPCLK
16 2
BRPRE
BR_VALUE 1
+
()
×
-----------------------------------------------------------------------------------
STEP
256
---------------
×
=