參數資料
型號: SAK-XC2220L-12F80V
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 80 MHz, RISC MICROCONTROLLER, PQCC48
封裝: 0.50 MM PITCH, GREEN, PLASTIC, VQFN-48
文件頁數: 35/112頁
文件大?。?/td> 3122K
代理商: SAK-XC2220L-12F80V
XC2220L, XC2224L
XC2000 Family / Econo Line
Functional Description
PRELIMINARY
Data Sheet
25
V1.0, 2010-12
3
Functional Description
The architecture of the XC222[04]L combines advantages of RISC, CISC, and DSP
processors with an advanced peripheral subsystem in a well-balanced design. On-chip
memory blocks allow the design of compact systems-on-silicon with maximum
performance suited for computing, control, and communication.
The on-chip memory blocks (program code memory and SRAM, dual-port RAM, data
SRAM) and the generic peripherals are connected to the CPU by separate high-speed
buses. Another bus, the LXBus, connects additional on-chip resources and external
resources (see Figure 3). This bus structure enhances overall system performance by
enabling the concurrent operation of several subsystems of the XC222[04]L.
The block diagram gives an overview of the on-chip components and the advanced
internal bus structure of the XC222[04]L.
Figure 3
Block Diagram
DPRAM
CPU
PM
U
DMU
ADC0
Module
8-/10- /
12 -Bit
RTC
MCHK
Interrupt & PEC
LXBUS
Controller
DSRAM
System Functions
Clock, Reset, Power
Control
OCDS
Debug Support
Interrupt Bus
Per
ip
h
er
al
D
at
a
Bu
s
Analog and Digital General Purpose IO (GPIO) Ports
MC_L-SERIES_BLOCKDIAGRAM
GPT
5
Timers
CC2
Module
16
Chan.
LX
B
us
WWD
Multi
CAN
CCU6 x
Modules
3+1
Chan.
each
USICx
Modules
2
Chan.
each
PSRAM
Flash Memory
IM
B
MAC Unit
MPU
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