參數(shù)資料
型號： SAK-C509-LM
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 16 MHz, MICROCONTROLLER, PQFP100
封裝： PLASTIC, MQFP-100
文件頁數(shù)： 24/74頁
文件大小： 1607K
代理商： SAK-C509-LM
Semiconductor Group
29
09.96
C509-L
Table 4
Special Function Registers - Functional Blocks
Block
Symbol
Name
Address
Contents after
Reset
CPU
ACC
B
DPH
DPL
DPSEL
PSW
SP
SYSCON1
Accumulator
B-Register
Data Pointer, High Byte
Data Pointer, Low Byte
Data Pointer Select Register
Program Status Word
Stack Pointer
System Control Register 1
E0H
1)
F0H
1)
83H
82H
92H
D0H
1)
81H
B2H
00H
00H
XXXXX000B
3)
00H
07H
00XXXEE0B
3)6)
SFR
Mapping
SYSCON 2) System Control Register
B1H
1010XX01B
3)
Interrupt
System
IEN0
CTCON 2)
CT1CON 2)
IEN1 2)
IEN2 2)
IEN3
IP0 2)
IP1 2)
IRCON0
IRCON1
IRCON2 4)
EICC1 4)
TCON 2)
T2CON 2)
Interrupt Enable Register 0
Compare Timer Control Register
Compare Timer 1 Control Register
Interrupt Enable Register 1
Interrupt Enable Register 2
Interrupt Enable Register 3
Interrupt Priority Register 0
Interrupt Priority Register 1
Interrupt Request Control Register 0
Interrupt Request Control Register 1
Interrupt Request Control Register 2
Interrupt Request Enable Register for CT1
Timer Control Register
Timer 2 Control Register
A8H
1)
E1H
BCH
B8H
1)
9AH
BEH
A9H
B9H
C0H
1)
D1H
BFH
88H
1)
C8H
1)
00H
01000000B
3)
X1XX0000B
3)
00H
XX0000X0B
3)
XXXX00XXB
3)
00H
0X000000B
3)
00H
00H
FFH
00H
XRAM
XPAGE
SYSCON 2)
Page Address Register for XRAM
System Control Register
91H
B1H
00H
1010XX01B
3)
A/D
Converter
ADCON0
ADCON1
ADDATH
ADDATL
A/D Converter Control Register 0
A/D Converter Control Register 1
A/D Converter Data Register, High Byte
A/D Converter Data Register, Low Byte
D8H
1)
DCH
D9H
DAH
00H
01000000B
3)
00H
1)
Bit-addressable special function registers
2)
This special function register is listed repeatedly since some bits of it also belong to other functional blocks.
3)
X means that the value is indeterminate or the location is reserved
4)
Register is mapped by bit PDIR.
5)
Register is mapped by bit RMAP.
6)
“E” means that the value of the bit is defined by the logic level at pin PRGEN at the rising edge of the RESET
or HWPD signals
.
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