參數(shù)資料
型號： SAFC163-L
廠商： SIEMENS AG
元件分類： 圓形連接器
英文描述： Circular Connector; No. of Contacts:37; Series:MS27467; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:15; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:15-35 RoHS Compliant: No
中文描述： 16位CMOS單片機
文件頁數(shù)： 38/68頁
文件大?。?/td> 625K
代理商： SAFC163-L
11Aug98@14:48h Intermediate Version
Semiconductor Group
36
1998-08
C163-L
Phase Locked Loop
For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is
enabled and provides the CPU clock (see table above). The PLL multiplies the input frequency by
the factor
F
which is selected via the combination of pins P0.15-13 (i.e. f
CPU
= f
OSC
*
F
). With every
F
’th transition of f
OSC
the PLL circuit synchronizes the CPU clock to the input clock. This
synchronization is done smoothely, i.e. the CPU clock frequency does not change abruptly.
Due to this adaptation to the input clock the frequency of f
CPU
is constantly adjusted so it is locked
to f
OSC
. The slight variation causes a jitter of f
CPU
which also effects the duration of individual TCLs.
The timings listed in the AC Characteristics that refer to TCLs therefore must be calculated using the
minimum TCL that is possible under the respective circumstances.
The actual minimum value for TCL depends on the jitter of the PLL. As the PLL is constantly
adjusting its output frequency so it corresponds to the applied input frequency (crystal or oscillator)
the relative deviation for periods of more than one TCL is lower than for one single TCL (see formula
and figure below).
For a period of
N
* TCL the minimum value is computed using the corresponding deviation D
N
:
(
N
* TCL)
min
=
N
* TCL
NOM
- D
N
where
N
= number of consecutive TCLs
D
N
[ns] =
±
(13.3 +
N
*6.3) / f
CPU
[MHz],
and 1
≤
N
≤
40.
So for a period of 3 TCLs @ 25 MHz (i.e.
N
= 3): D
3
= (13.3 +
3
* 6.3) / 25 = 1.288 ns,
and (3TCL)
min
= 3TCL
NOM
- 1.288 ns = 58.7 ns (@ f
CPU
= 25 MHz).
This is especially important for bus cycles using waitstates and e.g. for the operation of timers, serial
interfaces, etc. For all slower operations and longer periods (e.g. pulse train generation or
measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is neglectible.
Note:
For all periods longer than 40 TCL the N=40 value can be used (see figure below).
Figure 11
Approximated Maximum Accumulated PLL Jitter
Note:
The PLL only operates within the standard supply voltage range of V
DD
= 4.5 - 5.5 V.
40
20
10
5
1
±
1
±
10
±
20
N
This approximated formula is valid for
1
≤
N
≤
40 and 10MHz
≤
f
CPU
≤
25MHz.
±
26.5
Max.jitter D
N
[ns]
20 MHz
25 MHz
16 MHz
10 MHz
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參數(shù)描述
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