參數(shù)資料
型號(hào): SAFC161O
廠商: INFINEON TECHNOLOGIES AG
英文描述: 16-Bit Single-Chip Microcontroller
中文描述: 16位單片機(jī)
文件頁數(shù): 16/66頁
文件大小: 1102K
代理商: SAFC161O
C161K
C161O
Data Sheet
12
V2.0, 2001-01
Central Processing Unit (CPU)
The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic
and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a
separate multiply and divide unit, a bit-mask generator and a barrel shifter.
Based on these hardware provisions, most of the C161K/O
s instructions can be
executed in just one machine cycle which requires 80 ns at 25 MHz CPU clock. For
example, shift and rotate instructions are always processed during one machine cycle
independent of the number of bits to be shifted. All multiple-cycle instructions have been
optimized so that they can be executed very fast as well: branches in 2 cycles, a 16
×
16
bit multiplication in 5 cycles and a 32-/16 bit division in 10 cycles. Another pipeline
optimization, the so-called
Jump Cache
, allows reducing the execution time of
repeatedly performed jumps in a loop from 2 cycles to 1 cycle.
Figure 4
CPU Block Diagram
MCB02147
CPU
SP
STKOV
STKUN
Instr. Reg.
Instr. Ptr.
Exec. Unit
4-Stage
Pipeline
MDH
MDL
PSW
SYSCON
Context Ptr.
Mul/Div-HW
Bit-Mask Gen
R15
R0
General
Purpose
Registers
Barrel - Shifter
ALU
(16-bit)
Data Page Ptr.
Code Seg. Ptr.
Internal
RAM
R15
R0
ROM
16
16
32
BUSCON 0
BUSCON 1
BUSCON 2
BUSCON 3
BUSCON 4
ADDRSEL 4
ADDRSEL 3
ADDRSEL 2
ADDRSEL 1
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