參數(shù)資料
型號： SAF-XC2287M-72F80LAA
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： RISC MICROCONTROLLER, PQFP144
封裝： 0.50 mm pitch, GREEN, PLASTIC, LQFP-144
文件頁數(shù)： 39/142頁
文件大?。?/td> 1112K
代理商： SAF-XC2287M-72F80LAA
XC2287M, XC2286M, XC2285M
XC2000 Family Derivatives / Base Line
Electrical Parameters
Data Sheet
133
V2.0, 2009-03
4.6.7
Debug Interface Timing
The debugger can communicate with the XC228xM either via the 2-pin DAP interface or
via the standard JTAG interface.
Debug via JTAG
The following parameters are applicable for communication through the JTAG debug
interface. The JTAG module is fully compliant with IEEE1149.1-2000.
Note: These parameters are not subject to production test but verified by design and/or
characterization.
Note: Operating Conditions apply.
Table 37
JTAG Interface Timing Parameters for Upper Voltage Range
Parameter
Symbol
Values
Unit Note /
Test Condition
Min.
Typ.
Max.
TCK clock period
t
1 SR
50
––ns
1)
1) Under typical conditions, the JTAG interface can operate at transfer rates up to 20 MHz.
TCK high time
t
2 SR
16
––ns
TCK low time
t
3 SR
16
––ns
TCK clock rise time
t
4 SR
–
–8ns
TCK clock fall time
t
5 SR
–
–8ns
TDI/TMS setup
to TCK rising edge
t
6 SR
6
––ns
TDI/TMS hold
after TCK rising edge
t
7 SR
6
––ns
TDO valid
after TCK falling edge2)
2) The falling edge on TCK is used to generate the TDO timing.
t
8 CC
–
2529ns
TDO high imped. to valid
from TCK falling edge2)3)
3) The setup time for TDO is given implicitly by the TCK cycle time.
t
9 CC
–
2529ns
TDO valid to high imped.
from TCK falling edge2)
t
10 CC
–
2529ns
TDO hold after
TCK falling edge2)
t
18 CC
5
––ns
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