參數(shù)資料
型號: SAF-XC2264N-16F40L
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 40 MHz, RISC MICROCONTROLLER, PQFP100
封裝: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-100
文件頁數(shù): 98/131頁
文件大?。?/td> 1627K
代理商: SAF-XC2264N-16F40L
XC2261N/68N, XC2263N/64N/65N
XC2000 Family / Value Line
Functional Description
Data Sheet
69
V1.4, 2011-07
3.19
Power Management
The XC226xN provides the means to control the power it consumes either at a given time
or averaged over a certain duration.
Three mechanisms can be used (and partly in parallel):
Supply Voltage Management permits the temporary reduction of the supply voltage
of major parts of the logic or even its complete disconnection. This drastically reduces
the power consumed because it eliminates leakage current, particularly at high
temperature.
Several power reduction modes provide the best balance of power reduction and
wake-up time.
Clock Generation Management controls the frequency of internal and external
clock signals. Clock signals for currently inactive parts of logic are disabled
automatically. The user can drastically reduce the consumed power by reducing the
XC226xN system clock frequency.
External circuits can be controlled using the programmable frequency output
EXTCLK.
Peripheral Management permits temporary disabling of peripheral modules. Each
peripheral can be disabled and enabled separately. The CPU can be switched off
while the peripherals can continue to operate.
Wake-up from power reduction modes can be triggered either externally with signals
generated by the external system, or internally by the on-chip wake-up timer. This
supports intermittent operation of the XC226xN by generating cyclic wake-up signals.
Full performance is available to quickly react to action requests while the intermittent
sleep phases greatly reduce the average system power consumption.
Note: When selecting the supply voltage and the clock source and generation method,
the required parameters must be carefully written to the respective bit fields, to
avoid unintended intermediate states. Recommended sequences are provided
which ensure the intended operation of power supply system and clock system.
Please refer to the Programmer’s Guide.
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